• Nuclear Engineering and Technology
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• v.44 no.6
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• pp.697-708
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• 2012

The majority of instrumentation and control (I&C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I&C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I&C systems. Therefore, existing NPPs are replacing the obsolete analog I&C systems with advanced digital systems. New NPPs are also adopting digital I&C systems because the economic efficiencies and usability of the systems are higher than the analog I&C systems. Digital I&C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.314-321
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• 2020

Logic automated stimulus and response (LASAR) software is an automatic test program development tool for logic function test and fault detection of avionics components digital circuit cards. LASAR software needs to the information for the logic circuit function and input and output of the device. If there is no component information, normal component modeling is impossible. In this paper, component modeling is carried out through reverse design of programmable logic device (PLD) device without element information. The developed LASAR program identified failure detection rates through fault simulation results and single-seated fault insertion methods. Fault detection rates have risen by 3% to 91% for existing limited modeling and 94% for modeling through the reverse design. Also, the 22 case of stuck fault with the I/O pin of EP310 PLD were detected 100% to confirm the good performance.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.6
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• pp.45-54
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• 2004

Usually, according as accumulation degree of semi-conductor element increases, dynamic mistake test time increases sharply, and use of pattern generator is essential at manufacturing process to solve these problem. In this paper, we designed the PLD(Programmable Logic Device) circuit of pattern generator to examine dynamic mistake of semi-conductor element. Such all item got result that is worth verified action of return trip and function through simulation, and satisfy.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.11a
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• pp.191-196
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• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.3
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• pp.48-54
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• 2004

We have developed a new experimental driving system in order to make an easier drive experiment of PDP. By using the system, we can design and simulate the timing of the pulse in computer environment. As a result of the designed timing, we are able to program at PLD(Programmable Logic Device) and control high-voltage FET switches. The new system can reduce the time of the pulse compared with the previous logic gate ICs that realizes switching logic through hardware. In addition, it is a much easier way of changing the timing of the pulse due to the change of the driving method. By using the developed driving system we experimented on two different things- First, the realization of ADS Driving Method that run commonly; Second, gray scale realization on the three electrodes AC PDP.

• Journal of Sensor Science and Technology
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• v.12 no.1
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• pp.44-50
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• 2003

A security system consisted of an infrared sensor and PLD(Programmable Logic Device) was fabricated to prevent an intruder. The fabricated system detect the intruder using infrared sensor and has password key pad to permit someone to enter the house and office. The control circuit of the system is designed by VHDL(Very high speed integrated Hardware Description Language). The system was demonstrated in various conditions and the output signals were displayed in LCD, LED, buzzer and so on. This designed system in this paper has a advantage to supplement additional function with ease.

• The Journal of Engineering Research
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• v.6 no.1
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• pp.111-124
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• 2004

The advanced semiconductor technology and electronic design automation(EDA) tools make it possible to implement the system on the programmable logic devices. The electronic design method is also changing from schematic capture to hardware description language. In this paper, I present the architecture of multi-dimensional digital filter which can be efficiently implemented on PLDs. This is based on the former research results which are called algorithm decomposition technique. Algorithm decomposition technique is used to obtain the computational primitive from the state space equations of the multi-dimensional digital filtering algorithm. The obtained computational primitive is designed with VHDL. This can be used to implement the filtering system as a component. The designed filtering system is implemented on the PLD. Therefore, the filter can be upgradable on system. It is greatly reduced the time-to-market time of the system that is based on the multi-dimensional filter.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1143-1145
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• 2000

In this paper, it presents the design and implementation of a Microstep control IC using Programmable Logic Device(PLD). A Microstep driver is implemented with a 5-phase hybrid stepping motor, which has a Pentagon winding, power MOSFETs, and some devices to improve the system characteristics. The Microstep driving method is used for high performance motion control, low vibration and low noise in motor control system. The improvement of the electrical and mechanical driving characteristic of a step motor is achieved by applying microstep driver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1189-1199
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• 2003

This paper presents a new method for the motion detection of vehicles using hierarchical motion estimation and parallel processing. It captures the road image by using a CMOS sensor. It divides the captured image into small blocks and detects the motion of each block by using a block-matching method which is based on a hierarchical motion estimation and parallel processing for the real-time processing. The parallelism is achieved by using tile pipeline and the data flow technique. The proposed method has been implemented by using an embedded system. The proposed block matching algorithm has been implemented on PLDs(Programmable Logic Device) and clustering algorithm has been implemented by ARM processor. Experimental results show that the proposed system detects the motion of vehicles in real-time.