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A Design of High Performance Parallel CRC Generator  

Lee, Hyun-Bean (한양대학교 멀티미디어 시스템 연구실)
Park, Sung-Ju (한양대학교 멀티미디어 시스템 연구실)
Min, Pyoung-Woo (한양대학교 멀티미디어 시스템 연구실)
Park, Chang-Won (전자부품연구원 유비쿼터스컴퓨팅 연구센터)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.29, no.9A, 2004 , pp. 1101-1107 More about this Journal
Abstract
This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.
Keywords
CRC(Cyclic Redundancy Check); Parallel CRC; Logic Optimization; XOR Gate;
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  • Reference
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