• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.240-243
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• 1999

This paper presents a data-dependent precharge suppression(DPS) D-flip-flop(DFF) with precharge suppression scheme according to data-transition probability The main feature of the DPS DFF is that precharge is suppressed when there is no data transition. The proposed DPS DFF consumes less power than the conventional Yuan-Svensson's true single phase clocking(TSPC) DFF when the data-transition probability is low. The simulation result shows that the power consumption is reduced by 42.2 % when the data-transition probability is 30%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.699-702
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• 1998

This paper presents a 500MHz 1.1㎱ 32kb synchronous CMOS SRAM macro using $0.35\mu\textrm{m}$ CMOS technology. In order to operate at high frequency and reduce power dissipation, the designed SRAM macro is realized with optimized decoder, multi-point sense amplifier(MPSA), selective precharge scheme and etc. Optimized decorder and MPSA respectively reduce 50% and 40% of delay time. Also, a selective precharge scheme reduces 80% of power dissipation in that part.

• 한국대기환경학회지
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• 제15권4호
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• pp.463-473
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• 1999

The main purpose of this study is to investigate the characteristics of precharge electro-cyclone compared to those of innercharge electro-cyclone, experimentally. Especially, the experiment is executed focusing on the improvement of collection efficiency with the charging types including the experimental parameters such as the discharge electrode shapes, applied voltages and gas inlet velocities. Results show that the overall collection efficiency of precharge electro-cyclone is increased over 20% than that of the innercharge type for the same discharge electrode(ø 4 mm, screw rod) in the inlet velocity of 4 m/s, and applied voltage of 30kV. Moreover, the pressure drop of precharge type becomes 10% lower than that of the innercharge type for the inlet velocity of 12 m/s owing to the disturbance of inner vortex flow by the discharge electrode equipped in the center region of cyclone body.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.583-584
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• 2008

This paper presents a low-power and high-speed pulsed flip-flop based on dual-precharging and conditional discharging. The dual-precharging operation minimizes the parasitic capacitance of each precharge node, resulting in high-speed operation. The conditional-discharging operation minimizes the redundant transitions of precharge nodes, resulting in low-power operation. Linear feedback shift register (LFSR) designed in a $0.18{\mu}m$ CMOS technology using the proposed flip-flop achieves 32% power reduction as compared to conventional design.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1555-1557
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• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.742-744
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• 1999

In this paper, a new precharge type PFD for fast locking time of PLL is suggested. It is realized by inserting NMOS transistor and inverter into the precharge part of PFD for isolating the reset of the Up signal from the feedback signal. The new precharge type PFD generates the Up signal while the feedback signal is fixed at a high level. Therefore the new PFD output is increased than the conventional precharge type PFD output. As a result of the increased PFD output, fast locking of PLLs is achieved. Additionally, with control the falling time of the inverter, the dead-zone is reduced and the jitter characteristics are improved. The whole characteristics of PFD and PLL are simulated by using HSPICE. Simulation results show that the dead-zone is 20ps and the locking time of PLL using the new PFD is 38ns at the 350MHz frequency of referecne signal. This value is quite small compared with conventional PFD.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3088-3090
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• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.

• 한국전자통신학회논문지
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• 제18권5호
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• pp.769-776
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• 2023

본 논문에서는 저 전력 CAM(: Content Addressable Memory)을 위한 MLSA(: Match-line Sense Amplifier)를 설계하였다. 설계한 회로는 MLSA와 사전충전 (precharge) 제어기를 통해 선택적 매치라인 충전기법으로 CAM 동작 중 미스매치 상태에서 발생하는 전력 소모를 감소시켰고, 검색동작 중 미스매치가 발생했을 때 사전 충전을 조기 종료시킴으로써 단락 전류로 인한 전력 소모를 추가적으로 감소시켰다. 기존 회로와 비교했을 때, 전력 소모와 전파 지연 시간이 6.92%, 23.30% 감소하였고, PDP(: Product-Delay-Product)와 EDP(: Energy Delay Product)가 29.92%, 52.31% 감소하는 우수한 성능을 보였다. 제안한 회로는 TSMC 65nm CMOS 공정을 사용하여 구현되었으며 SPECTRE 시뮬레이션을 통해 그 타당성을 입증하였다.

• 대한전자공학회논문지SD
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• 제40권11호
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• pp.45-53
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• 2003

DRAM에서 사용되는 내부 승압 전원 전압과 기판인가 전원 전압 발생기를 공유함으로써 단일 Charge Pump에서 승압 전원과 기판 전원을 동시에 발생시키는 회로를 설계하였다. 이 회로는 0.14um의 DRAM 공정을 사용하여 기존 보다 전력 소모를 30%, 전체 면적을 40% 그리고 Pumping capacitor 면적을 29.6% 각각 감소하였으며 또한 전류 공급 효율을 13.2% 향상 시켰다. Charge Recycling 기법을 적용하여 Pumping capacitor의 Precharge 구간 동안 소모되는 전류를 75% 감소하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.271-274
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• 2001

In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$ ∼ $\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.