• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.625-631
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• 2014

We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a $60{\times}30{\mu}m^2$ active area.

• ETRI Journal
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• 제30권5호
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• 한국정보통신학회논문지
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• 제16권8호
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• pp.1734-1740
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• 2012

본 논문에서는 단일전원을 사용하는 PMIC 칩이 패키지 상태에서 eFuse OTP 메모리를 프로그램 가능하도록 스위칭 전류가 작은 FSOURCE 회로를 제안하였다. 제안된 FSOURCE 회로는 non-overlapped clock을 사용하여 short-circuit current를 제거하였으며, 구동 트랜지스터의 ON되는 기울기를 줄여 최대 전류를 줄였다. 그리고 power-on reset 모드동안 eFuse OTP의 출력 데이터를 임의의 데이터로 초기화시키는 DOUT 버퍼 회로를 제안하였다. $0.35{\mu}m$ BCD 공정을 이용하여 설계된 24비트 differential paired eFuse OTP 메모리의 레이아웃 면적은 $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$)이다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.400-402
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• 2008

A new interleaved forward converter, adopting series-input parallel-output structure with a common transformer reset circuit, is proposed in this paper. Series-input structure distributes the voltage stress on switches, which makes it suitable for high input voltage application. Paralleling output stage with an interleaving technique enables the circuit handle large output current and reduces filter size. In addition, since two forward converters share one active-clamp circuit for the transformer reset, its primary structure is simplified. All these features make the proposed converter promising for high input voltage applications with high efficiency and simple structure.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.685-688
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• 2005

플라즈마 디스플레이를 위한 효율적인 서스테인 드라이버와 이를 리셋 회로와 결합시키는 유용한 결합 방법을 제시한다. 제안된 서스테인 드라이버는 외부 인덕터와 패널에 존재하는 기생 커페시터 간의 직렬공진 방식을 이용한다. 이 회로는 4개의 스위칭 소자, 인덕터, 전원공급을 목적으로 하는 외부 커패시터로 구성된다. 기존의 방식과 비교하여 입력전원전압이 두배가 되지만 스위칭 소자에 가해지는 전압스트레스는 기존의 값과 거의 동일하며, 입력 전압을 별도의 승압없이 리셋 회로의 전원으로 사용할 수 있는 장점을 가진다. 이러한 회로적 구조는 서스테인 드라이버와 리셋회로를 간단히 구성할 수 있다. 이론적 분석을 바탕으로 동작원리와 설계 예를 제시하며, 7.5인치 AC PDP 패널을 이용한 실험을 통해 타당성을 검증한다.

• Journal of Power Electronics
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• 제8권2호
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• pp.148-155
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• 2008

In this paper, a cost-effective PDP driving circuit using the transformer network is proposed. Compared with the previous works, the half-bridge type energy recovery circuit recovers the reactive energy not to the capacitor but to the source. A single sustain board architecture removes the blocking switches which are placed on the discharge path in parallel, thus reducing the number of devices. A simple reset circuit generates the same waveforms as the previous approaches. The circuit configuration and modified driving waveforms are compared with the previous works. The validity of the proposed simplified driver is verified through tests using a 6-inch panel.

• 센서학회지
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• 제17권1호
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• pp.41-52
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• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 추계학술대회 논문집
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• pp.215-217
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• 2007

Recently, the demand for high definition TV is being increased by beginning of the digital broadcasting. The higher resolution of PDP is, the longer addressing time become, then, the sustain period for display image decreases. Because of the reason, dual-scan method which synchronously write information of an image on top and bottom of the screen is used for the high definition PDP. However, as the price competition of PDP becomes severe, we can`t avoid turning to a single-scan method which uses only a half of an expensive address IC. Accordingly, the sustain period becomes much shorter than prior method. In case of XGA level, it is impossible to display, eventually. In this paper, we are going to prove usefulness by realizing negative reset waveform and the driving circuit for high speed addressing.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권9호
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• pp.467-475
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• 1999

This paper presents an analysis method of a forward converter, using both the finite element method considering the external circuit and a state variables equation. The converter operates at 50kHz and its one period is divided into two modes for the simplicity of the analysis. In the first mode, the switching transistor turns on and an input power is transferred into the load by the electromagnetic conversion action of a ferrite transformer. In the second mode, the switching transistor turns off and the stored energy in an inductor is delivered to the load, and the transformer core is demagnetized by the reset winding current. In this paper, time-stepping finite element method taking into account the on-state electrical circuit of the converter in used to analyze both the electrical circuit and electromagnetic field of the magnetic device during the first mode and the demagnetization period of the transformer core. Then a state variables equation for the circuit which the inductor current flows is constituted and solved during the second mode. As a result, the simulation results have been good agreement with the results obtained form experiment.

• Transactions on Electrical and Electronic Materials
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• 제11권1호
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.