• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.443-450
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• 2016

The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 1992년도 추계학술대회논문집; 반도아카데미, 20 Nov. 1992
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• pp.81-86
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• 1992

원자력발전소 1차 계통 내의 건전성 감시를 위한 설비로는 음향누설 감시계 통(Acoustic Leak Monitoring System: ALMS), 금속파편 감시계통(Loose Parts Monitoring System: LPMS) 및 원자로내부구조물 진동감시계통 (Internals Vibration Monitoring System: IVMS)등이 있다. 현재, 국내의 여 러 원전에는 이들중 일부 계통들이 선택적으로 설치되어 운전중이며, 영광 3,4호기에서는 국내 최초로 이들 3개의 계통을 종합한 핵증기공급계통 건전 성감시계통(Nuclear Steam Supply System Integrity Monitoring System: NIMS)을 설계하였다. 특히, 영광 3,4호기 NIMS에서는 각 계통에 의해 감지 된 1차 계통 내의 이상상태를 하나의 분석컴퓨터(Analysis Computer)를 사 용하여 해석하는 종합결함 탐지해석 기법을 도입하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.650-656
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• 2016

Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.

• Journal of Electrical Engineering and Technology
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• 제6권6호
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• pp.817-823
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• 2011

This paper introduces an efficient voltage multiplier circuit for improved voltage gain and power efficiency of radio frequency identification (RFID) tags. The multiplier is fully integratable and takes advantage of both passive and active circuits to reduce the required input power while yielding the desired DC voltage. A six-stage voltage multiplier and an ultralow power voltage regulator are designed in a 0.13 ${\mu}m$ complementary metal-oxide semiconductor process for 2.45 GHz RFID applications. The minimum required input power for a 1.2 V supply voltage in the case of a 50 ${\Omega}$ antenna is -20.45 dBm. The efficiency is 15.95% for a 1 $M{\Omega}$ load. The regulator consumes 129 nW DC power and maintains the reference voltage in a 1.1% range with $V_{dd}$ varying from 0.8 to 2 V. The power supply noise rejection of the regulator is 42 dB near a 2.45 GHz frequency and performs better than -32 dB from 100 Hz to 10 GHz frequencies.

• 한국정보전자통신기술학회논문지
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• 제15권5호
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• pp.335-342
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• 2022

본 논문에서는 오디오 애플리케이션을 위한 단일 비트 3차 피드포워드 델타 시그마 변조기를 제안한다. 제안된 변조기는 저전압 및 저전력 애플리케이션을 위한 클래스-C 인버터를 기반으로 한다. 고정밀 요구 사항을 위해 레귤레이티드 캐스코드 구조의 클래스-C 인버터는 DC 이득을 증가시키고 저전압 서브쓰레스홀드 증폭기 역할을 한다. 제안된 클래스-C 인버터 기반 변조기는 180nm CMOS 공정으로 설계 및 시뮬레이션되었다. 성능 손실이 없으면서 낮은 공급 전압 호환성을 가지도록 제안된 클래스-C 인버터 기반 스위치드 커패시터 변조기는 높은 전력 효율을 달성하였다. 본 설계는 20kHz의 신호 대역폭 및 4MHz의 샘플링 주파수에서 동작시켜 93.9dB의 SNDR, 108dB의 SNR, 102dB의 SFDR 및 102dB의 DR를 달성하면서 0.8V 전원 전압에서 280μW의 전력 소비만 사용한다.

• 한국소음진동공학회논문집
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• 제11권7호
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• pp.253-260
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• 2001

A Study of interior noise reduction in the magelv train is presented. Tarin speed of interest is low such that aero-dynamic noise is negligible and power supply system is a dominant noise source. Based on the measurements of interior noise and acceleration levels during running and zero speed conditions, dominant noise sources are identified. After spectra characteristics of noise sources are investigated several noise reducing methods are studied such as STL increasement of floor panels. sealing. and absorption treatment It is found that the most important noise sources are VVVF inverter and SLM in running condition, whereas air conditioner and DC/DC converter are dominant in zero speed. Sine the major noise sources are under the floor complete sealing and high STL of the floor panel are shown to be the most crucial factors in noise reduction After sound absorbing material, which is polyurethan foam of 50 mm thickness, is thickness, is attached to the downward side of the floor in addition to sealing treatment, the interior noise is reduced by 3~4 dB.

• 한국전자파학회논문지
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• 제15권1호
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• pp.68-72
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• 2004

InGaP/GaAs HBT공정을 이용하여 1.75 ㎓의 전압제어 발진기를 설계한다. 전압제어 발진기의 위상 잡음을 개선하기 위하여 저역 통과 필터의 특성을 가지는 새로운 잡음 제거 회로를 제안하고, 극 소형화를 위하여 FR-4 기판의 특수한 적층 구조를 이용한다. 제작된 전압제어 발진기의 주파수 변화 범위는 약 200 MHz이고, 위상 잡음은 120 KHz 옵？에서 -119.3 ㏈c/Hz이다. VCO 코어의 소비 전력은 공급 전원 2.8 V에서 11.2 ㎽이고, 출력 파워는 -2 ㏈m이다. FOM의 계산치는 191.7로써, 지금까지 발표된 FET나 HBT 전압제어 발진기보다 좋은 성능을 보인다. 완성된 전압제어 발진기의 크기는 3.266 mm ${\times}$ 3.186 mm로 극소형이다.

• 조명전기설비학회논문지
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• 제12권4호
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• pp.146-154
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• 1998

교류 전원선로에서 발생하는 수 kHz에서 수십 MHz에 이르는 광대역의 주파수특성올 가진 전원노이즈는 전기, 전자장비의 정상적인 동작에 많은 장해요소가 되고 있으며 이들 전도노이즈를 억제하기 위한 부품으로 현재 써어지 억제부품과 필터가 적용되고 있다. 그러나 기존의 대책부품은 전력공급선과 노이즈 피해회로를 전기적으로 완전히 절연시킬 수 없기 때문에 전도 노이즈 중에서 가장 크게 발생하는 공통모드 노이즈 억제성능이 제한 되고 있다. 본 논문에서는 절연변압기의 절연 특성에 정전 차폐를 추가함으로써 전도노이즈 및 써어지 억제기능이 우수한 NCf의 설계방법올 제시하였으며, 설계 제작된 1[kVA] NCT 시작품의 모의 등가회로에 대한 써어지 해석결과와 실험 측정 결과를 상호 비교하여 제안된 모델의 특성을 비교 평가하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권1호
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• pp.53-76
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• 2020

The synchronous phasor measurement algorithm is the core content of the phasor measurement unit. This manuscript proposes a dynamic synchronous phasor measurement algorithm based on compressed sensing theory. First, a dynamic signal model based on the Taylor series was established. The dynamic power signal was preprocessed using a least mean square error adaptive filter to eliminate interference from noise and harmonic components. A Chirplet overcomplete dictionary was then designed to realize a sparse representation. A reduction of the signal dimension was next achieved using a Gaussian observation matrix. Finally, the improved orthogonal matching pursuit algorithm was used to realize the sparse decomposition of the signal to be detected, the amplitude and phase of the original power signal were estimated according to the best matching atomic parameters, and the total vector error index was used for an error evaluation. Chroma 61511 was used for the output of various signals, the simulation results of which show that the proposed algorithm cannot only effectively filter out interference signals, it also achieves a better dynamic response performance and stability compared with a traditional DFT algorithm and the improved DFT synchronous phasor measurement algorithm, and the phasor measurement accuracy of the signal is greatly improved. In practical applications, the hardware costs of the system can be further reduced.

• Journal of Power Electronics
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• 제11권4호
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• pp.591-598
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• 2011

This paper investigates a power supply of medium voltage with enhanced ignition characteristics for plasma torches. A series resonant half-bridge topology is presented as a suitable ignition circuitry. The ignition circuitry is integrated into the main power conversion system of a multi-phase staggered three-level dc-dc converter with a diode front-end rectifier. A plasma torch rated at 3MW, 2kA and having a physical size of 1m is selected to be the high enthalpy source for a waste disposal system. The steady-state and transient operations of a plasma torch are simulated. The parameters of a Cassie-Mary arc model are calculated based on 3D magneto-hydrodynamic simulations. The circuit simulation waveform shows that the ripple of the arc current can be maintained within ${\pm}10%$ of its rated value under the presence of a load disturbance. This power conversion configuration provides a high enough ignition voltage, around 5KA, during the ignition phase and high arc stability under the existence of arc disturbance noise resulting in a high-performance plasma torch system.