• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2273-2280
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• 2013

This article introduces the next-generation air surveillance system and investigates how to design of front-end low noise amplifier of the ground station receiver. In consideration of the international standard documentation and the performance of existing products, the study conducts the link budget on the entire system so that it can be competitive in terms of receive sensitivity or reliability. To obtain a proper low noise amplifier, standards of design are decided so that such factors as gain, gain flatness, and reflective loss can be optimal. In its design, the bias circuit appropriate for the characteristics of low power, low noise, or high gain was built, and according to the results of the simulation conducted after the optimal design, its gain was 16.24dB, noise factor was 0.36dB, input-output reflective loss was -18dB and -28dB each, and frequency stability was 1.11. According to the results measured after the design, its gain was 17dB, noise factor was 0.51dB, gain flatness was 0.23dB, and input-output reflective loss was -18.28dB and -24.50dB each, so the results gained were suitable for building the overall system.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.3
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• pp.102-110
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• 2005

Piezoelectric transformers(PT) are expected to be small, thin and highly efficient, and which are attractive as a transformer with high power density for step down voltage. For these reasons, we have attempted to develop a step-down PT for the miniaturized adaptor. We propose a PT, operating in thickness extensional vibration mode for step-down voltage. This PT consists of a multi-layered construction in the thickness direction. In order to develop the step-down PT of 10 W class and turn ratio of 0.1 with high efficiency and miniaturization, the piezoelectric ceramics and PT designs are estimated with a variety of characteristics. The basic composition of piezoelectric ceramics consists of ternary yPb(Zr$_{x}$Ti$_{1-x}$)O$_{3}$-(1-y)Pb(Mn$_{1/3}$Nb1$_{1/3}$Sb$_{1/3}$)O$_{3}$. In the piezoelectric characteristics evaluations, at y=0.95 and x=0.505, the electromechanical coupling factor(K$_{p}$) is 58$\%$, piezoelectric strain constant(d$_{33}$) is 270 pC/N, mechanical quality factor(Qr$_{m}$) is 1520, permittivity($\varepsilon$/ 0) is 1500, and Curie temperature is 350 $^{\circ}C$. At y = 0.90 and x = 0.500, kp is 56$\%$, d33 is 250 pC/N, Q$_{m}$ is 1820, $\varepsilon$$_{33}$$^{T}$/$\varepsilon$$_{0}$ is 1120, and Curie temperature is 290 $^{\circ}C$. It shows the excellent properties at morphotropic phase boundary regions. PZT-PMNS ceramic may be available for high power piezoelectric devices such as PTs. The design of step-down PTs for adaptor proposes a multi-layer structure to overcome some structural defects of conventional PTs. In order to design PTs and analyze their performances, the finite element analysis and equivalent circuit analysis method are applied. The maximum peak of gain G as a first mode for thickness extensional vibration occurs near 0.85 MHz at load resistance of 10 .The peak of second mode at 1.7 MHz is 0.12 and the efficiency is 92$\%$.

• Nuclear Engineering and Technology
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• v.56 no.3
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• pp.803-811
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• 2024

Nuclear accidents such as Fukushima Daiichi have highlighted the potential of passive safety systems to replace or complement active safety systems as part of the overall prevention and/or mitigation strategies. In addition, passive systems are key features of Small Modular Reactors (SMRs), for which they are becoming almost unavoidable and are part of the basic design of many reactors available in today's nuclear market. Nevertheless, their potential to significantly increase the safety of nuclear power plants still needs to be strengthened, in particular the ability of computer codes to determine their performance and reliability in industrial applications and support the safety demonstration. The PASTELS project (September 2020-February 2024), funded by the European Commission "Euratom H2020" programme, is devoted to the study of passive systems relying on natural circulation. The project focuses on two types, namely the SAfety COndenser (SACO) for the evacuation of the core residual power and the Containment Wall Condenser (CWC) for the reduction of heat and pressure in the containment vessel in case of accident. A specific design for each of these systems is being investigated in the project. Firstly, a straight vertical pool type of SACO has been implemented on the Framatome's PKL loop at Erlangen. It represents a tube bundle type heat exchanger that transfers heat from the secondary circuit to the water pool in which it is immersed by condensing the vapour generated in the steam generator. Secondly, the project relies on the CWC installed on the PASI test loop at LUT University in Finland. This facility reproduces the thermal-hydraulic behaviour of a Passive Containment Cooling System (PCCS) mainly composed of a CWC, a heat exchanger in the containment vessel connected to a water tank at atmospheric pressure outside the vessel which represents the ultimate heat sink. Several activities are carried out within the framework of the project. Different tests are conducted on these integral test facilities to produce new and relevant experimental data allowing to better characterize the physical behaviours and the performances of these systems for various thermo-hydraulic conditions. These test programmes are simulated by different codes acting at different scales, mainly system and CFD codes. New "system/CFD" coupling approaches are also considered to evaluate their potential to benefit both from the accuracy of CFD in regions where local 3D effects are dominant and system codes whose computational speed, robustness and general level of physical validation are particularly appreciated in industrial studies. In parallel, the project includes the study of single and two-phase natural circulation loops through a bibliographical study and the simulations of the PERSEO and HERO-2 experimental facilities. After a synthetic presentation of the project and its objectives, this article provides the reader with findings related to the physical analysis of the test results obtained on the PKL and PASI installations as well an overall evaluation of the capability of the different numerical tools to simulate passive systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Nuclear Engineering and Technology
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• v.48 no.5
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• pp.1273-1279
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• 2016

Production of iodine-131 by neutron activation of tellurium in tellurium dioxide ($TeO_2$) material requires a target that meets the safety requirements. In a radiopharmaceutical production unit, a new lid for a can was designed, which permits tight sealing of the target by using tungsten inert gaswelding. The leakage rate of all prepared targets was assessed using a helium mass spectrometer. The accepted leakage rate is ${\leq}10^{-4}mbr.L/s$, according to the approved safety report related to iodine-131 production in the TRIGA Mark II research reactor (TRIGA: Training, Research, Isotopes, General Atomics). To confirm the resistance of the new design to the irradiation conditions in the TRIGA Mark II research reactor's central thimble, a study of heat effect on the sealed targets for 7 hours in an oven was conducted and the leakage rates were evaluated. The results show that the tightness of the targets is ensured up to $600^{\circ}C$ with the appearance of deformations on lids beyond $450^{\circ}C$. The study of heat transfer through the target was conducted by adopting a one-dimensional approximation, under consideration of the three transfer modes-convection, conduction, and radiation. The quantities of heat generated by gamma and neutron heating were calculated by a validated computational model for the neutronic simulation of the TRIGA Mark II research reactor using the Monte Carlo N-Particle transport code. Using the heat transfer equations according to the three modes of heat transfer, the thermal study of I-131 production by irradiation of the target in the central thimble showed that the temperatures of materials do not exceed the corresponding melting points. To validate this new design, several targets have been irradiated in the central thimble according to a preplanned irradiation program, going from4 hours of irradiation at a power level of 0.5MWup to 35 hours (7 h/d for 5 days a week) at 1.5MW. The results showthat the irradiated targets are tight because no iodine-131 was released in the atmosphere of the reactor building and in the reactor cooling water of the primary circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.74-81
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• 2007

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.1
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• pp.15-22
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• 2008

In this paper, we propose a numerical analysis on reversed current of distributed amplifier based on transmission line theory and proposed a theory to obtain optimum transmission line length to minimize the reversed currents by cancelling those components. The reversed current is analyzed as being simply absorbed into the terminal resistance in the conventional analysis. In the proposed analysis, however, they are designed to be cancelled by each other with opposite phase by the optimal length of the transmission lint Circuit simulation and implementation using pHEMT transistor were performed to validate the proposed theory with the cutoff frequency of 3.6 GHz. From the measurement, maximum gain of 14.5dB and minimum gain of 12.3dB were achieved In the operation band. Moreover, measured efficiency of the proposed distributed amplifier is 25.6% at 3 GHz, which is 7.6%, higher than the conventional distributed amplifier. Measured output power Is about 10.9dBm, achieving 1.7dB higher output power than the conventional one. Those improvement is thought to be based on the cancellation of refersed current.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.758-765
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• 2018

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a $14{\times}$ frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves >10 dBm output power from 23.8 to 24.36 GHz and the phase noise is -97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output $P_{1dB}$ of -31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of $1.63{\times}1.6mm^2$. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a $4{\times}4$ patch array with 14.76 dBi gain and receiving antennas are two $4{\times}2$ patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.

• Journal of IKEEE
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• v.24 no.3
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• pp.859-866
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• 2020

This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage V_POS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage V_NEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates V_POS voltages of 4.6 V and V_NEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.