• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.495-498
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• 2002

This paper describes the results the problem of stress calculation and optimization into a FRP(Fiber-glass Reinforced Plastic) tube crimped into a metal end-fitting. This type of assembly is used mainly is used mainly for suspension and line post insulators. Fitting strength of FRP and flange of this study is required greatly from composite insulator to important special quality. Therefore, wish to seek analysis and mechanical strength performance that follow to FRP tube and flange of top and bottom mechanical fitting.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.556-557
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• 2005

The distribution facilities, such as suspension insulator, line post insulator, lightning arrester, COS, used for long periods in the industrial pollution area were investigated. The electrical test and the material analyses were performed on the polluted and non-polluted facilities. The low frequency dry flashover voltage of polluted suspension was decreased about 8% in comparison with non-polluted one. The polluted materials turned out with the iron which came from the foundries. The polluted materials turned out with the iron which came from the foundries. This conductive materials decreased the leakage distance, resulting in reducing of electrical properties.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1490-1491
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• 2007

The salt contamination on the distribution facilities, such as suspension insulator, line post insulator, lightning arrester, COS, is one of the major coastal areas because more than 90% of salt contaminated failure occurs in distribution facilities. Did to stain distribution facilities artificially according to Equivalent Salt Deposit Density(ESDD) grade. The electrical test were performed on the non-polluted and polluted facilities(ESDD B, C, D grade).

• 한국세라믹학회지
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• 제37권11호
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• pp.1051-1057
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• 2000

TiO$_2$와 CeO$_2$박막을 Si 위에 증착한 후 MOCVD법에 의해 PbTiO$_3$박막을 증착하여 MFIS 구조를 형성하였다. 절연층의 후열처리가 절연층 및 MFIS 구조의 전기적 특성에 미치는 영향을 관찰하기 위해 산소분위기와 $600^{\circ}C$~90$0^{\circ}C$의 온도범위에서 후 열처리를 행하였고, C-V 특성 및 누설전류 특성을 분석하였다. CeO$_2$와 TiO$_2$박막의 유전상수는 증착 직후 6.9와 15였으며, 90$0^{\circ}C$ 열처리를 행한 후 약 4.9와 8.8로 감소하였다. 누설전류밀도 역시 증착 직후 각각 7$\times$$10^{-5}$ A/$ extrm{cm}^2$와 2.5$\times$$10^{-5}$ A/$\textrm{cm}^2$에서 90$0^{\circ}C$ 열처리를 거친 후에 약 4$\times$$10^{-8}$ A/$\textrm{cm}^2$와 4$\times$$10^{-9}$ A/$\textrm{cm}^2$로 감소하였다. Ellipsometry 시뮬레이션을 통해 계산된 계면층의 두께는 90$0^{\circ}C$에서 약 115$\AA$(CeO$_2$) 및 140$\AA$(TiO$_2$)까지 증가하였다. 계면층은 MFIS 구조에서 강유전층에 인가되는 전계를 감소시켜 항전계를 증가시켰고, charge injection을 방지하여 Al/PbTiO$_3$/CeO$_2$(90$0^{\circ}C$, $O_2$)/Si 구조의 경우 $\pm$2 V~$\pm$10 V의 측정범위에서 memory window가 계속 증가하는 것을 보여주었다.

• 전기전자학회논문지
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• 제22권3호
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• pp.706-711
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• 2018

본 논문에서는 플라즈마 화학기상증착 (plasma enhanced chemical vapor deposition, PECVD) 방식을 이용한 산질화규소(Silicon oxynitride, SiON) 절연체를 이용하여 4H-SiC metal-oxide-semiconductor (MOS) 소자를 제작하고 특성 분석을 수행하였다. 제작된 소자는 금속 증착 후 열처리 과정 (post metallization annealing, PMA)을 통하여 트랩 밀도가 크게 감소하는 것을 확인하였으며, 특히 $500^{\circ}C$의 forming gas 분위기에서 열처리 된 소자의 경우 매우 뛰어난 MOS 특성을 나타내었다. 본 연구를 통하여 4H-SiC MOS 구조를 위한 대체 게이트 절연체로써 PECVD SiON의 활용 가능성을 확인 할 수 있었다.

• 대한전기학회논문지:전력기술부문A
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• 제49권8호
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• pp.390-398
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• 2000

Leakage impulse current of the contaminated insulators by using experiment data were studied. The impulse current in phase-time relationship was analyzed on line post insulators. Also, frequency components and crest factor of the leakage current were investigated to provide a scheme for an early detection of insulator incipient failure. The study shows that the phase-time characteristic is non-stationary and random and, non-harmonic component and crest factor can be promising parameters for detecting insulator leakage currents.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 E
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• pp.1670-1674
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• 1998

Now and then there are many electrical accidents between cable and line post insulator which is degraded by long time using, causing leakage current on the surface of insulator. In this paper it is denied that the 22.9 KV-y distribution lines are protected by binding cover which is needed from fog or rainy moisture, surges occurring by swiching or lightening pulse. It is analyzed to investgate the unballanced transfer characteristics and reflection coefficient by using bidding cover and non-cover. It was tested the radio interference voltage in the test room. In the factory it was tested the amount of leakage current causing on the surface of insulator in the state of no load and 70(%) load.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1871-1873
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• 2000

There are many electrical accidents between bare wire and line post insulator which is degraded by long time using, causing leakage current on the surface of insulator. In this paper it is presented that the 22.9 Kv-y distribution lines are protected by binding cover which is needed from fog or rainy moisture, surges occurring by switching or lightening pulse. It is analyzed to investigate the unbalanced transfer characteristics and reflection coefficient by using binding cover and non-cover. It was tested the radio interference voltage in the test room and electric field strength by calculation between binding cover and non-cover. In the factory the leakage current causing on the surface of insulator was tested in the state of light load and heavy load.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• 한국세라믹학회지
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• 제42권9호
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• pp.624-630
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• 2005

To investigate the possibility of the $ZrO_2$ buffer layer as the insulator for the Metal-Ferroelectric-Insulator-semiconductor (MFIS) structure, $ZrO_2$ and $SrBi_2Ta_2O_9$ (SBT) thin films were deposited on the P-type Si(111) wafer by the R.F. magnetron-sputtering method. According to the process with and without the post-annealing of the $ZrO_2$ buffer layer and SBT thin film, the diffusion amount of Sr, Bi, Ta elements show slight difference through the Glow Discharge Spectrometer (GDS) analysis. From X-ray Photoelectron Spectroscopy (XPS) results, we could confirm that the post-annealing process affects the chemical binding condition of the interface between the $ZrO_2$ thin film and the Si substrate. Compared to the MFIS structure without the post-annealing of the $ZrO_2$ buffer layer, memory window value of MFlS structure with post-annealing of the $ZrO_2$ buffer layer were considerably improved. The window memory of the Pt/SBT (260 nm, $800^{\circ}C)/ZrO_2$ (20 nm) structure increases from 0.75 to 2.2 V under the applied voltage of 9 V after post-annealing.