• 제목/요약/키워드: Polycrystalline silicon

검색결과 344건 처리시간 0.029초

AMOLED 디스플레이의 박막트랜지스터 제작을 위한 결정화 기술 동향 및 대형화 연구 (Trend of Crystallization Technology and Large Scale Research for Fabricating Thin Film Transistors of AMOLED Displays)

  • 김경보;이종필;김무진;민영실
    • 융합정보논문지
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    • 제9권5호
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    • pp.117-124
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    • 2019
  • 본 논문에서는 AMOLED 디스플레이 구동회로로 사용되는 박막트랜지스터의 구성요소 중에서 반도제 물질 제조의 최근 동향에 대해 논한다. 트랜지스터에 적용을 위해 특성이 좋은 반도체 막을 얻는 방법으로 비정질 실리콘을 다결정 실리콘으로 변화시켜야 하는데 레이저와 열처리 방법이 있으며, 레이저를 이용한 기술에는 SLS(Sequential Lateral Solidification), ELA(Excimer Laser Annealing), TDX(Thin-beam Directional Crystallization), 열처리 기술에는 SPC(Solid Phase Crystallization), SGS(Super Grain Silicon), MIC(Metal Induced Crystallization), FALC(Field Aided Lateral Crystallization)가 대표적이며, 이들에 대해 상세히 설명한다. 본 연구실에서 연구중인 레이저 결정화 기술의 대형 AMOLED 디스플레이 제작을 위한 연구 내용도 다룬다.

폴리이미드 기판에 극저온 Catalytic-CVD로 제조된 니켈실리사이드와 실리콘 나노박막 (Nano-thick Nickel Silicide and Polycrystalline Silicon on Polyimide Substrate with Extremely Low Temperature Catalytic CVD)

  • 송오성;최용윤;한정조;김건일
    • 대한금속재료학회지
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    • 제49권4호
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    • pp.321-328
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    • 2011
  • The 30 nm-thick Ni layers was deposited on a flexible polyimide substrate with an e-beam evaporation. Subsequently, we deposited a Si layer using a catalytic CVD (Cat-CVD) in a hydride amorphous silicon (${\alpha}$-Si:H) process of $T_{s}=180^{\circ}C$ with varying thicknesses of 55, 75, 145, and 220 nm. The sheet resistance, phase, degree of the crystallization, microstructure, composition, and surface roughness were measured by a four-point probe, HRXRD, micro-Raman spectroscopy, FE-SEM, TEM, AES, and SPM. We confirmed that our newly proposed Cat-CVD process simultaneously formed both NiSi and crystallized Si without additional annealing. The NiSi showed low sheet resistance of < $13{\Omega}$□, while carbon (C) diffused from the substrate led the resistance fluctuation with silicon deposition thickness. HRXRD and micro-Raman analysis also supported the existence of NiSi and crystallized (>66%) Si layers. TEM analysis showed uniform NiSi and silicon layers, and the thickness of the NiSi increased as Si deposition time increased. Based on the AES depth profiling, we confirmed that the carbon from the polyimide substrate diffused into the NiSi and Si layers during the Cat-CVD, which caused a pile-up of C at the interface. This carbon diffusion might lessen NiSi formation and increase the resistance of the NiSi.

플라스틱 기판위에 엑시머 레이저 열처리된 저온 다결정 실리콘 박막 트랜지스터 (Low Temperature Poly-Si TFTs with Excimer Laser Annealing on Plastic Substrates)

  • 최광남;곽성관;김동식;정관수
    • 전자공학회논문지 IE
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    • 제43권2호
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    • pp.11-15
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    • 2006
  • FPD (flat panel display)의 능동구동 (active matrix) 방식의 플렉시블 디스플레이를 위해 PES의 플라스틱 기판위에 극저온 다결정 실리콘 박막 트랜지스터를 제작하였다. 상온에서도 박막의 증착이 가능한 RF 마크네트론 스퍼터링과 양질의 다결정 실리콘 박막을 얻을 수 있다고 알려진 XeCl 엑시머 레이져 열처리를 이용하였으며 모든 공정이 150$^{\circ}C$ 이하의 극저온에서 이루어졌다. 플라스틱 기판에 형성한 실리콘 박막 트랜지스터는 344 $mJ/cm^2$ 의 에너지 밀도에서 결정화 하였을 때 이동도 63.64$cm^2/V$ 로 기판에 회로를 집적할 수 있기에 충분한 특성을 얻을 수 있었다.

나노급 두께의 Ni50Co50 복합 실리사이드의 적외선 흡수 특성 연구 (IR Absorption Property in NaNo-thick Nickel Cobalt Composite Silicides)

  • 송오성;김종률;최용윤
    • 대한금속재료학회지
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    • 제46권2호
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    • pp.88-96
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    • 2008
  • Thermal evaporated 10 nm-$Ni_{50}Co_{50}$/(70 nm-poly)Si films were deposited to examine the energy saving properties of silicides formed by rapid thermal annealing at temperature ranging from 500 to $1,100^{\circ}C$ for 40 seconds. Thermal evaporated 10 nm-Ni/(70 nm-poly)Si films were also deposited as a reference using the same method for depositing the 10 nm-$Ni_{50}Co_{50}$/(70 nm-poly)Si films. A four-point probe was used to examine the sheet resistance. Transmission electron microscopy (TEM) and X-ray diffraction XRD were used to determine cross sectional microstructure and phase changes, respectively. UV-VIS-NIR and FT-IR (Fourier transform infrared spectroscopy) were used to examine the near-infrared (NIR) and middle-infrared (MIR) absorbance. TEM analysis confirmed that the uniform nickel-cobalt composite silicide layers approximately 21 to 55 nm in thickness had formed on the single and polycrystalline silicon substrates as well as on the 25 to 100 nm thick nickel silicide layers. In particular, nickel-cobalt composite silicides showed a low sheet resistance, even after rapid annealing at $1,100^{\circ}C$. Nickel-cobalt composite silicide and nickel silicide films on the single silicon substrates showed similar absorbance in the near-IR region, while those on the polycrystalline silicon substrates showed excellent absorbance until the 1,750 nm region. Silicides on polycrystalline substrates showed high absorbance in the middle IR region. Nickel-cobalt composite silicides on the poly-Si substrates annealed at $1,000^{\circ}C$ superior IR absorption on both NIR and MIR region. These results suggest that the newly proposed $Ni_{50}Co_{50}$ composite silicides may be suitable for applications of IR absorption coatings.

Zeta 전위에 의한 도핑되지 않은 다결정 Si 및 GaAs 반도체 계면의 표면준위에 관한 정성적 해석 (A Qualitative Analysis on the Surface States at the Undoped Polycrystalline Si and GaAs Semiconductor Interfaces Using the Zeta Potential)

  • Chun, Jang-Ho
    • 대한전자공학회논문지
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    • 제24권4호
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    • pp.640-645
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    • 1987
  • Surface states and interfacial phenomena at the undoped polycrystalline semiconductor particale-electrolyte interfaces were qualitatively analyzed based on the zeta potentials which were measured with microelectrophoresis measurements. The suspensions were composed of the undoped polycrystaline silicon(Si) or gallium arsenide (GaAs) semiconductor particles stalline Si and GaAs particles in the KCl electrolytes was 3.73~6.2x10**-4 cm\ulcornerV.sec and -2.3~1.4x10**-4cm\ulcornerV.sec at the same conditions, respectively. The range of zeta potentials corresponding to the electrophoretic mobilities is 47.8~80.1mV and -30.1~17.9mV, respectively. The variation of the zeta potentials of the undoped polycrystalline Si was similar to the doped crystalline Si. On the other hand, two points of zeta potential reversal occurred at the undoped polycrystalline GaAs-KCl electrolyte interfaces. The surface states of the undoped polycrystalline Si and GaAs were dominated by positively charged donor surface states. These surface states are attributed to adsorbed ion surface states (slow states) at the semiconductor oxide layer-electrolyte interfaces.

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Application of Modified Rapid Thermal Annealing to Doped Polycrystalline Si Thin Films Towards Low Temperature Si Transistors

  • So, Byung-Soo;Kim, Hyeong-June;Kim, Young-Hwan;Hwang, Jin-Ha
    • 한국재료학회지
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    • 제18권10호
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    • pp.552-556
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    • 2008
  • Modified thermal annealing was applied to the activation of the polycrystalline silicon films doped as p-type through implantation of $B_2H_6$. The statistical design of experiments was successfully employed to investigate the effect of rapid thermal annealing on activation of polycrystalline Si doped as p-type. In this design, the input variables are furnace temperature, power of halogen lamps, and alternating magnetic field. The degree of ion activation was evaluated as a function of processing variables, using Hall effect measurements and Raman spectroscopy. The main effects were estimated to be furnace temperature and RTA power in increasing conductivity, explained by recrystallization of doped ions and change of an amorphous Si into a crystalline Si lattice. The ion activation using rapid thermal annealing is proven to be a highly efficient process in low temperature polycrystalline Si technology.

A Study on Blister Formation and Electrical Characteristics with Varied Annealing Condition of P-doped Amorphous Silicon

  • 최성진;김가현;강민구;이정인;김동환;송희은
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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    • pp.346.2-346.2
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    • 2016
  • The rear side contact recombination in the crystalline silicon solar cell could be reduced by back surface field. We formed polycrystalline silicon as a back surface field through crystallization of amorphous silicon. A thin silicon oxide applied to the passivation layer. We used quasi-steady-state photoconductance measurement to analyze electrical properties with various annealing condition. And, blister formed on surface of wafer during the annealing process. We observed the blister after varied annealing process with wafer of various surface. Shape and density of blister is influenced by various annealing temperature and process time. As the annealing temperature became higher, the average diameter of blister is decreased and total number of blister is increased. The sample with the $600^{\circ}C$ annealing temperature and 1 min annealing time exhibited the highest implied open circuit voltage and lifetime. We predicted that the various shape and density of blister affects the lifetime and implied open circuit voltage.

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Crystallization of Amorphous Silicon Films Using Joule Heating

  • Ro, Jae-Sang
    • 한국표면공학회지
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    • 제47권1호
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    • pp.20-24
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    • 2014
  • Joule heat is generated by applying an electric filed to a conductive layer located beneath or above the amorphous silicon film, and is used to raise the temperature of the silicon film to crystallization temperature. An electric field was applied to an indium tin oxide (ITO) conductive layer to induce Joule heating in order to carry out the crystallization of amorphous silicon. Polycrystalline silicon was produced within the range of a millisecond. To investigate the kinetics of Joule-heating induced crystallization (JIC) solid phase crystallization was conducted using amorphous silicon films deposited by plasma enhanced chemical vapor deposition and using tube furnace in nitrogen ambient. Microscopic and macroscopic uniformity of crystallinity of JIC poly-Si was measured to have better uniformity compared to that of poly-Si produced by other methods such as metal induced crystallization and Excimer laser crystallization.

Plasma Oxidation Effect on Ultralow Temperature Polycrystalline Silicon TFT on Plastic Substrate

  • Kim, Yong-Hae;Moon, Jae-Hyun;Chung, Choong-Heui;Yun, Sun-Jin;Park, Dong-Jin;Lim, Jung-Wook;Song, Yoon-Ho;Lee, Jin-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.1122-1125
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    • 2006
  • The TFT performances were enhanced and stabilized by plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of $Al_2O_3$ gate dielectric film. We attribute the improvement to the formation of a high quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFT's characteristics, and is regulated by the gap distance between the electrode and the polycrystalline Si surface.

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