• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1836-1840
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• 2003

This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.9
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• pp.461-466
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• 1999

The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1643-1647
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• 2003

This paper, we propose a new high noise immunity phase-locked loop(PLL) which can suppress the high incident noise coupling with large amplitude and long period to the input frequency of PLL and keeps constant frequency and phase of the VCO output for providing the high stability distribution clock pulse.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.233-236
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• 2005

Phase noise in a phase-locked-loop (PLL) is unwanted and unavoidable. It is a main concern in oscillation system especially PLL. The phase noise is derived in term of power spectrum density by using a reliable phase noise model. There are four noise sources being considered in this paper, which are generated by reference oscillator, voltage controlled oscillator, filter, and main divider. The major concern for this paper is the noise from the filter. Two types of second order low pass filter are used in the PLL system. Applying the mathematical phase noise model, the output noises are compared. The total noise from the passive filter is lower than the active filter at the offset frequency range between 1 Hz to 33 kHz.

• International Journal of Control, Automation, and Systems
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• v.5 no.2
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• pp.161-169
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• 2007

The PLL equivalent augmented system incorporated with state feedback is proposed in this paper. The optimal value of filter time constant of loop filter in the phase-locked loop control system and the optimal state feedback gain designed by using linear quadratic regulator approach are derived. This approach allows the PLL control system to employ the large value of the phase-frequency gain $K_d$ and voltage control oscillator gain $K_o$. In designing, the structure of phase-locked loop control system will be rearranged to be a phase-locked loop equivalent augmented system by including the structure of loop filter into the process and by considering the voltage control oscillator as an additional integrator. The designed controller consisting of state feedback gain matrix K and integral gain $k_1$ is an optimal controller. The integral gain $k_1$ related to weighting matrices q and R will be an optimal value for assigning the filter time constant of loop filter. The experimental results in controlling the second-order lag pressure process using two types of loop filters show that the system response is fast without steady-state error, the output disturbance effect rejection is fast and the tracking to step changes is good.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.520-523
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• 2004

A phase-locked loop control system designed by using the linear quadratic regulator approach is presented in this paper. The system thus designed is optimal system when system is in locked state and the parameter value of loop filter which is an active PI filter can be obtained easily. By considering the structure of loop filter of phase-locked loop is included in the process to be controlled, a type 1 servo system can be constructed when voltage control oscillator is considered as an integrator. The integral gain of the proposed system obtained by linear quadratic regulator approach can be used as an optimal value to design the parameter of loop filter. The implemented result in controlling the second-order lag pressure process by using the proposed scheme show that the system response is fast with no overshoot and no steady-state error. Furthermore, the experimental results are also shown in term of output disturbance effect rejection, tracking and process parameter changed.

• ETRI Journal
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• v.29 no.4
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• Journal of Power Electronics
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• v.15 no.1
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• pp.65-77
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• 2015

Resonant converters are well suited for induction heating (IH) applications due to their advantages such as efficiency and power density. The control systems of these appliances should provide smooth and wide power control with fewer losses. In this paper, a simple phase locked loop (PLL) based variable duty cycle (VDC) pulse density modulation (PDM) power control scheme for use in class-D inverters for IH loads is proposed. This VDC PDM control method provides a wide power control range. This control scheme also achieves stable and efficient Zero-Voltage-Switching (ZVS) operation over a wide load range. Analysis and modeling of an IH load is done to perform a time domain simulation. The design and output power analysis of a class-D inverter are done for both the conventional pulse width modulation (PWM) and the proposed PLL based VDC PDM methods. The control principles of the proposed method are described in detail. The validity of the proposed control scheme is verified through MATLAB simulations. The PLL loop maintains operation closer to the resonant frequency irrespective of variations in the load parameters. The proposed control scheme provides a linear output power variation to simplify the control logic. A prototype of the class-D inverter system is implemented to validate the simulation results.