대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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위상고정 시간이 빠른 새로운 듀얼 슬로프 위상고정루프

A Fast Locking Phase-Locked Loop using a New Dual-Slope Phase Frequency Detector and Charge Pump Architecture

  • 박종하 (한양대학교 전자전기제어계측공학과) ;
  • 김훈 (한양대학교 전자전기제어계측공학과) ;
  • 김희준 (한양대학교 전자컴퓨터공학부)
  • Park, Jong-Ha (Department of Electronics, Electrical, Control and Instrumentation Engineering, Hanyang University) ;
  • Kim, Hoon (Department of Electronics, Electrical, Control and Instrumentation Engineering, Hanyang University) ;
  • Kim, Hee-Jun (School of Electronics and Computer Science, Hanyang University)
  • 발행 : 2008.05.25
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초록

본 논문은 고속 위상 고정이 가능한 새로운 듀얼 슬로프 위상고정루프를 제안한다. 기존의 듀얼 슬로프 위상고정루프는 각각 2개의 전하펌프와 위상 주파수 검출기로 구성되었다. 본 논문에서는 위상차에 따라 전하펌프의 전류를 조절해 하나의 전하펌프와 위상 주파수 검출기만으로 듀얼 슬로프 위상고정루프를 구현하였다. 제안된 회로는 $0.35{\mu}m$ CMOS 공정 파라미터 값으로 HSPICE 시뮬레이션을 수행하여 회로의 동작을 검증하였다. 제안된 듀얼 슬로프 위상고정루프의 위상 고정 시간은 $2.2{\mu}s$로 단일 슬로프 위상고정루프의 위상 고정 시간인 $7{\mu}s$보다 개선된 결과를 얻었다.

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

키워드

참고문헌

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