Phase Locked Loop based Pulse Density Modulation Scheme for the Power Control of Induction Heating Applications

Abstract

Resonant converters are well suited for induction heating (IH) applications due to their advantages such as efficiency and power density. The control systems of these appliances should provide smooth and wide power control with fewer losses. In this paper, a simple phase locked loop (PLL) based variable duty cycle (VDC) pulse density modulation (PDM) power control scheme for use in class-D inverters for IH loads is proposed. This VDC PDM control method provides a wide power control range. This control scheme also achieves stable and efficient Zero-Voltage-Switching (ZVS) operation over a wide load range. Analysis and modeling of an IH load is done to perform a time domain simulation. The design and output power analysis of a class-D inverter are done for both the conventional pulse width modulation (PWM) and the proposed PLL based VDC PDM methods. The control principles of the proposed method are described in detail. The validity of the proposed control scheme is verified through MATLAB simulations. The PLL loop maintains operation closer to the resonant frequency irrespective of variations in the load parameters. The proposed control scheme provides a linear output power variation to simplify the control logic. A prototype of the class-D inverter system is implemented to validate the simulation results.

I. INTRODUCTION

IH systems are used in many industrial, domestic and medical applications due to their high performance. IH technology takes advantage of contactless energy transfer to the work piece to obtain faster heating, improved safety, and higher efficiency than conventional heating methods. The core component of an IH system is the power supply. An IH power supply system is usually composed of a rectifier stage and a resonant inverter. Series resonant inverters (SRIs) are widely used as a high frequency source [1], [2]. In SRIs, the resonant tank circuit is formed by a work coil and a capacitor. A SRI fed with a voltage source represents a simple and cost-effective solution [3]-[5]. However, the output power of such an inverter is controlled by adjusting the DC input voltage. A controlled rectifier with a DC-link capacitor has been conventionally used to provide a variable DC voltage so that the output power of the inverter gets adjusted. However, the size and cost of this conventional arrangement is large [5]-[8]. To overcome these problems, the power control of an inverter, fed by an uncontrolled rectifier using frequency modulation, phase-shift variation and asymmetrical voltage cancellation control is discussed in many studies to regulate the output power. An important goal of power control is to achieve an efficient and useful product. Inverters with the above modulation schemes result in increased switching losses because it is impossible for the switching devices to be always turned on and off at zero current or zero voltage instants.

Generally, IH applications use a frequency modulation scheme to control the output power. Variable frequency control is a basic method which is used for variable load conditions. Variable frequency control is used for half bridge and full bridge SRIs [9]. However, pulse frequency modulation control causes many problems since the switching frequency has to be varied over a wide range to accommodate the worst combinations of loads. The efficiency of an inverter decreases significantly with an increase in the switching frequency to lower the output power. The major disadvantage of this method is the large frequency range requirement for a wide range of output power control. For a frequency below resonance, the filter components are bulky because they must be designed for the low frequency range. For operation above resonant frequency, fast switching devices are required to maintain control in the higher frequency range. In addition, the soft switching range of a frequency modulated high frequency inverter is relatively narrow. The control of a SRI with a constant switching frequency with a variable pulse width is one of the ways to avoid the problems of variable frequency control [10], [11].

Therefore, class-D inverter topologies using PWM control, phase-shift control and asymmetrical voltage control have been proposed. In fixed frequency operation, the inverter is operated at a constant frequency and control of the output power without variations in the frequency. However, these control requirements and operating characteristics increase the complexity of the design due to the fixed frequency switching requirement which limits their performance. Phase shifted PWM control was used for full bridge inverters to adjust the output power [12]-[14]. In a IH power supply system using a phase-shift PWM control, zero voltage switching (ZVS) operation is not possible under light load conditions. This control strategy cannot be used for half bridge inverters. Asymmetrical voltage control strategy is also used for the control of output power. It gives improved efficiency due to its constant switching frequency and ZVS operation [15].This method results in high turn on losses under low load conditions due to the NON-ZVS operation of the switches. A discontinuous mode power control scheme for loss minimization is also discussed in the literatures [15]-[18].

In the above papers, a power control scheme of IH loads with the ZVS operating condition in the whole load range is not discussed. This paper discusses a simple PLL based VDC PDM power control scheme of the variable power ZVS class-D inverters for IH applications. The aim of this study is to control the power over a wide load range under the ZVS condition to improve the output power of IH systems. In this paper, the power supply for induction heating (IH) systems based on a class-D SRI is described. The output power of the inverter is controlled using a VDC based PDM. When the inverter is operated at a switching frequency higher than its resonant frequency; it can maintain ZVS operation in the whole load range [19]-[21]. The effective parameters for the equivalent resistance and inductance of an IH load vary throughout the heating cycle [22], [23]. Thus, it becomes necessary to change the operating frequency of the inverter in order to maintain the resonance condition according to load variations. The presented control circuit employs a frequency tracking system to monitor load variations. The control circuit also employs a PDM pulse generation logic circuit which provides modulated gate signals to the gate drive circuitry at the tracked load resonant frequency. Under PDM, the switching losses are fixed and the total output power of the inverter gets increased. In the proposed scheme, the inverter operation at resonance is maintained such that the losses are at a minimum. This improves the efficiency of the IH system over a wide range of power. The proposed modulation technique with a frequency tracking system can achieve a linear output power variation which simplifies the control algorithm.

 

II. SYSTEM DESCRIPTION

A block diagram of an IH power supply system is shown in Fig. 1. The class-D inverter takes energy from the 50Hz AC input source through an uncontrolled rectifier. The DC voltage is converted into a high-frequency AC voltage by using the class-D inverter. Then, the inverter supplies a high-frequency current to the induction coil. To track the resonant frequency of the load, a phase locked loop (PLL) is used. At the tracked load frequency, PDM gate pulses are generated and applied to the switches.

Fig. 1.Block diagram of IH power supply system.

A. Characteristics and Modeling of an IH Load

An IH load consists of a work-coil and a work-piece. In IH systems, most of the work-pieces have a cylindrical shape. They are heated by being placed inside the work coil with one or more turns. In IH applications, a magnetic field is induced in the work coil. This causes eddy currents in the work piece. These eddy currents give rise to a heating effect. Most of the heat in the work-piece is generated by eddy currents. Basically, an IH load is a transformer representation of the electromagnetic induction action between the work coil (primary) and the load (secondary) as shown in Fig. 2(a). The transformer parameters are difficult to measure. Therefore, it is better to represent the IH load using a simplified model. The IH load can be modeled by means of a series combination of its equivalent resistance Req and inductance Leq as shown in Fig. 2(b). These parameters depend on several variables, including the shape of the heating coil, the distance between the work-piece and the IH coil, the temperature, the electrical conductivity and magnetic permeability, and the frequency.

Fig. 2.(a) Transformer equivalent circuit of IH load. (b) Equivalent series RL circuit of IH load.

In the transformer equivalent of an IH load, L1 is the self inductance of the work coil. L2 is the inductance in the secondary side of the IH load, M is the mutual inductance of the transformer, and R2 is the resistance of the IH load. The equivalent values of the IH system Req and Leq change with the geometry, load materials, temperature, and excitation frequency. A change in the parameters makes the output power control harder. For this reason, a complete analysis of the equivalent parameters Req and Leq of the IH system is provided here. The voltage equations of the transformer model of the IH load are given below:

where, ωS = 2 πfS

fs is the switching frequency, and ωS is the angular switching frequency. IL1 and VL1 are the current and voltage in the work coil, respectively.

The load current IL2 can be obtained from (2) which is given as:

Equations (1) and (3) give the following expression:

The real and imaginary parts of the above equation are represented as Req and Leq as given in the following equations (5) and (6):

The general time constant of the load (τ) is defined as:

Equation (7) can be estimated using equations (5) and (6) as:

since:

The mutual coupling co-efficient (K) for a coupled circuit is generally defined as:

Solving (6) and (10) yields the following expression:

In equation (11), K is expressed with Req , Leq and L1.

B. Analysis of a Class-D Inverter

Fig. 3(a) shows the configuration of the class-D inverter system for an IH load. The class-D inverter consists of two switches S1 and S2 and two resonant capacitors with a capacitance of Cr/2 and an IH load. When the inverter is fed with the DC input voltage S1 and S2 are alternately used to allow a high-frequency AC current to the IH coil. Fig. 3(b) shows the equivalent circuit model of the class-D inverter. The switches of the class-D inverter are operated at above the resonant frequency in order to achieve ZVS during turn off [24], [25]. Conventionally, class-D inverter switches are operated with pulse width modulated gate pulses. In this paper power control using PDM is discussed. The PDM inverter repeats “run and stop” in accordance with a control sequence to adjust its output voltage.

Fig. 3.(a) Circuit configuration of class-D inverter. (b) Equivalent circuit of class-D inverter.

For simulation study, an IH load is considered with an equivalent circuit of a series combination of resistance Req and inductance Leq. This series branch with Req and Leq in combination with Cr forms the resonant circuit. The output power analysis of the resonant circuit under the conventional PWM method for the class-D inverter can be described by the following parameters. The angular resonant frequency (ωr) of the series resonant circuit is given by:

where Cr is the capacitance of the resonant capacitor. The normalized angular switching frequency (ωn) is expressed as:

The characteristic impedance (Zo) of the IH load is:

The quality factor (QL) of the IH coil is given by:

The equivalent impedance (Zeq) of the resonant tank circuit is given by the following equations:

The output voltage of the class-D inverter connected to the IH load is Vo:

The fundamental component (Vo1) of the output voltage can be found from the Fourier analysis:

Where, the peak value of the output load voltage (Vm) is:

The load current (Io) through the resonant tank circuit is described by the following equation:

The phase angle (Ø) of the load current is:

Where, the peak value of the output load current (Im) is:

The conventional output power (Po) of the class-D inverter is given in the following equations:

In the conventional PWM method the output power is varied by varying duty cycle of the power switches. A desired output power (Pdesired) can be obtained by variation of the PWM control duty ratio (DPWM).

The DPWM is given by the following equation:

Where TON is the turn on time of the switch and T is the total time period. In the PWM control the soft switching range is very narrow since TON is varied to control the output power.

C. Design Procedure of the Circuit Constraints

The design of the class-D inverter and the IH load parameters are described in this section. For the output power Po, the equivalent resistance of the IH load is given by the following equation:

By the definition of the quality factor of the resonant circuit given in equation (15), the equivalent inductance Leq of the heating coil with QL of 1.28 is given by:

Finally, the calculation of the value of the resonant capacitor can be done as per equation (12), by the definition of the resonant frequency.

To reduce the switching losses during the turn off condition, a lossless snubber capacitor (Cs) is used with the switch. Typically, the class-D operation mode implies that Cs is much lower than Cr [25]-[28]. As a result, the switching waveforms in the inverter have a direct impact on all of the inverter losses. During the charge intervals, the output current can be considered constant, due to the small snubber capacitors used in the class-D inverter.

D. Power Consumption in the MOSFET Switches of the Class-D Inverter

Power losses in the power electronic switches include the conduction and switching losses. The switching losses can also be classified into turn-on and turn-off losses. The class-D inverter uses two MOSFETs with anti parallel diodes. The conduction and switching losses for the MOSFET and diode are analyzed below. The total power loss in the MOSFET (PM) is determined using the following equation:

PCM is the conduction loss in the MOSFET, and PSWM is the switching loss in the MOSFET. PCM is given by:

RD is the ON state resistance of the switch, SON is the on/off state of the switch, and IDrms is the rms value of the current through the MOSFET. The PSWM in the MOSFET is:

Vs is the on state voltage of the switch, Id is the instantaneous value of the switch current at the time of switching, toff is the turn off time of the switch, and fs is the switching frequency.

The total power loss (PD) in the anti parallel diode is:

PCD is the conduction loss in the diode, and PSWD is the switching losses in the diode. PCD is defined as:

VDO is the ON state voltage across the diode, and IF is average value of the forward current through the diode.

PSWD in the diode is given by:

where RD is the ON state resistance of the switch, and Ifrms is the rms value of the forward current through the diode. The total losses in the inverter module include the MOSFET and diode losses.

E. Analysis of the PDM Control Algorithm

Power control is an important goal to be achieved in an IH load to maintain a required temperature. The power input to the working coil of an IH load has to be controlled to control the heating of the work piece. Conventionally, this is achieved by the control of the class-D inverter using the PWM technique. In the conventional PWM based power control, the output power is controlled through DPWM. In the PWM scheme, DPWM is the control variable for continuous power regulation. A variation of DPWM causes a violation in the soft switching operation which leads to higher switching losses and reduced output power. A pulse modulation technique called VDC PDM with frequency tracking using a PLL for power control is proposed in this paper. The principle of the PDM is to control the switching of the inverter by the pulse density control method, in which the output power control is done through controlling the ratio of the continuous pulse-on signal and the continuous pulse-off signal.

The main advantage of PDM is its linear dependency on the on-time of the output power. The basic idea of the proposed PDM control is that, by assuming a control cycle of time (TPDM), the inverter transmits power to the load in TA time and it stops working in the remaining (TPDM-TA) time. Thus the output power is related to the impulse density. In this way the output power can be changed by changing the pulse density. The PDM based gate signals for switches S1 and S2 are shown in Fig.4. When compared with conventional PWM control operation, the PDM operation reduces the switching losses because the MOSFET is always turned on and off under zero voltage during resonant operation.

Fig. 4.Theoritical waveforms of gate pulses.

The output voltage and current waveforms of the class-D inverter with the PDM control are described in Fig.5 with the assumption that the quality factor of the resonant circuit is finite. Here, the TPDM of the PDM pattern is long enough to make the amplitude of the resonant current fluctuate. The envelope of the resonant current shows that the first-order response though the series resonant circuit is of a second-order system.

Fig. 5.Theoritical waveforms of output voltage and current with PDM control.

A power analysis of the class-D inverter with the PDM control is given below. The envelope of the resonant current (iE) is given by:

Im is the maximum current in full-power operation, and I is the initial value of the envelope iE. If QL is infinite, the amplitude of the resonant current is in proportion to the pulse density.

In the PDM, the average output power (P) is obtained by multiplying Vd and iE as, follows:

If the total time TPDM of the PDM operation is much smaller than the time constant (τ), the amplitude of the resonant current is in proportion to the pulse density. As a result, no fluctuation occurs in the amplitude of the resonant current. Thus, the output power is in proportion to the square of the pulse density, as given by:

When TPDM>>τ, the output power is in proportion to the pulse density because the resonant current becomes a discontinuous waveform.

The effective IH load power is adjusted by controlling the ratio between the “on” and “off” periods. The PDM duty cycle (DPDM) is given by the following equation:

A desired output power can be obtained by a variation of DPDM. The term DPDM is also called a modulation index or pulse density, and its value determines the output power. In this paper DPDM is considered as a control variable. The desired power (Pdesired) for different load conditions can be obtained as follows:

In this paper, the maximum output power of the high frequency inverter is obtained for a modulation index value equal to one.

 

III. CONTROL SCHEME

It is necessary to operate an inverter close to the resonant frequency to achieve a reduction in the switching losses. An IH load is modeled by means of a series combination of its equivalent resistance Req and inductance Leq. These parameters depend on several variables, including the shape of the heating coil, the distance between the work-piece and the IH coil, the temperature, the electrical conductivity, the magnetic permeability, and the frequency. When the load parameters change, there is a change in the resonant condition. It becomes necessary to vary the inverter switching frequency during operation due to changes in the parameters which depend on the resonant frequency of the load circuit. Therefore, the control circuit should employ a frequency tracking system to track the resonant frequency of the newly changed parameters. A tuned frequency tracking system using a phase locked loop (PLL) is used to accomplish the above performance. When a work piece of a different metal is inserted into the IH coil, its geometry, conductivity and permeability cause the inductance of the heating coil to change. Considering the fact that the resonant capacitance is fixed, the tank circuit is driven to its new resonant frequency by tracking the switching frequency of the inverter. The PLL circuit can track the resonant frequency due to its fast dynamic response. Fig. 6 shows a block diagram of the PLL based control circuit developed for the PDM inverter. The proposed control circuit and its detailed operation are explained here. There are three parts that make up the control circuit.

Fig. 6.Block diagram of control scheme for class-D inverter.

Fig.7.DPDM control signal and gate pulses to S1 and S2.

At start up the DPDM is set to unity. Under that condition, the VCO which defines the working frequency of the inverter generates a frequency above the resonant frequency of the load. After this, the control voltage of the VCO gets changed until the working frequency of the inverter is close to the resonant frequency of the new load. The PDM modulation is performed continuously by the feedback loop. As the ZVS condition is guaranteed by the VCO loop, the PDM modulator adjusts the output power.

 

IV. DISCUSSIONS OF THE SIMULATION AND EXPERIMENTAL RESULTS

The validity of the proposed scheme was verified by the simulation and experimental results obtained on a prototype of an IH system. For the simulation a schematic of a class-D inverter and the control circuit have been implemented for time domain simulation using MATLAB. Since the inverter output power depends on the pulse density of the gate signals, a study of the efficiency of the PDM inverter for different values of DPDM must be made.

The design specifications and circuit parameters used for the class-D inverter for an IH load using commercial MOSFET and diode modules are listed in Table I. The parameters are designed according to the considerations given in the previous sections. In Table I it is shown that the switching frequency is greater than the resonant frequency to achieve the ZVS condition. A simulation of a class-D inverter using the proposed scheme is performed with a variation of the load power from 10% to 100% by varying DPDM from 10% to 100%. A high switching frequency (fs) of 25 kHz is chosen and a low frequency (fPDM) of 25 Hz is chosen to avoid acoustic noise. The simulation is carried out for different values of DPDM.

TABLE ISPECIFICATIONS OF CLASS-D INVERTER AND IH LOAD SYSTEM

For verification of the rated output power, the DPDM control signal is generated at 100% of the duty cycle as shown in Fig. 8(a). The simulated result of the output voltage under a full load is shown in Fig. 8(b). A zoomed view of the output voltage is given in Fig. 8(c). Under the full load condition, the output current flows continuously due to the 100% DPDM as shown in Fig. 8(d). A zoomed view of Io is given in Fig. 8(e). The output power corresponding to the 100% DPDM is shown in Fig. 8(f). It can be observed that for a modulation index value equal to one, the maximum output power of the inverter is obtained. Gate pulses are generated with a DPDM of 50% of the duty cycle. The corresponding control signal is shown in Fig. 9(a). The simulated results of Vo and Io at a 50% DPDM are shown in Figs. 9(b) and 9(c), respectively. It can be observed from the waveforms that Vo and Io are discontinuous in nature. When DPDM is 50%, the average current gets lower due to the discontinuous flow of Io. This causes a decrement in the average output power as shown in Fig. 9(d). There are no current spikes because the high frequency and low frequency PDM switching signals are synchronized at the on and off time.

Fig. 8.(a) DPDM control signal for 100% DPDM. (b) Output voltage with 100% DPDM. (c) Zoomed view of the output voltage with 100% DPDM. (d) Output current with 100% DPDM. (e) Zoomed view of the output current with 100% DPDM. (f) Output power with 100% DPDM.

Fig. 9.(a) Control signal for 50% DPDM. (b) Output voltage with 50% DPDM. (c) Output current with 50% DPDM. (d) Output power with 50% DPDM.

The DPDM control signal at 10% is shown in Fig. 10(a). The simulated results of Vo and a zoomed view of Vo at a 10% DPDM are shown in Figs. 10(b) and 10(c), respectively. The corresponding output current Io and a zoomed view are shown in Figs. 10(d) and 10(e), respectively. With a 10% DPDM, the average output power still gets decreased due to the discontinuous flow of Io.

Fig. 10.(a) Control signal for 10% DPDM. (b) Output voltage with 10% DPDM. (c) Zoomed view of output voltage with 10% DPDM. (d) Output current with 10% DPDM. (e) Zoomed view of output current with 10% DPDM. (f) Average output power with 10% DPDM.

Since the switchting frequency is maintained closer to the resonant frequency of the load by the PLL, even with the change in DPDM from 10% to 100%, ZVS of the switch can be achieved during the turn off condition. This can be observed from Figs. 11(a) and 11(b). In both of the waveforms, the rise in the switch current takes place during the zero state of the switch voltage. These waveforms ensure the ZVS turn off operating condition under any power level achieved with variations of the control variable DPDM. Due to the ZVS condition, the switching losses are reduced. This validates the proposed PLL based VDC PDM control strategy applied to a IH system.

Fig.11.(a) Switch voltage (Vs1) and switch current (is1) at 100% DPDM (b) Switch voltage (Vs1) and switch current (is1) at 10% DPDM.

To validate the proposed scheme in a class-D inverter circuit, an experimental laboratory setup was fabricated. The class-D inverter is supplied using a full bridge diode rectifier. The rectifier was constructed using four IN5408 diode switches. The class-D inverter was constructed using two power switches for DC-AC conversion. The power switches were MOSFETs (IRF840) which can withstand a maximum voltage and current of 500V and 8A, respectively.

An IH load was built by using a coil having an outer diameter of 110mm and a thickness of 8mm. A work-piece of 100*45mm has been chosen as the heating load. The control circuit for the IH system is implemented with the PDM control strategy using a PIC16F877A micro controller. The hardware layout of the system is shown in Fig. 12(a). The VDC PDM scheme is validated with this hardware setup for a DPDM of 100% and 10%. For a 100% DPDM, high frequency pulses are allowed to the switches without modulation as shown in Fig. 12(b).

Fig. 12.(a) Hardware layout of the prototype. (b) DPDM control signal(100%) and high frequency PWM pulses (0.5v/div,0.01s/div). (c) Experimental output voltage at 100% DPDM (20V/div,0.05μs/div). (d) Experimental output current at 100% DPDM (2A/div,1μs/div).

The experimental output voltage and output current at a 100% DPDM are shown in Figs. 12(c) and 12(d), respectively, where Vo and Io continuously deliver the rated output power. The DPDM control signal at 10% and the high frequency signals are shown in Fig 13(a). The switching pulses for switches S1 and S2 are shown in Fig 13(b). These pulses are driven through a gate driver circuit (IR2110) to the switches. With the same PDM control signal, the experimental output voltage is shown in Fig. 13(c). The experimental output current at a 10% DPDM is shown in Fig. 13(d).

Fig. 13.Experimental results at 10% DPDM. (a) DPDM control signal and high frequency switching signal (1V/div, 0.01s/div) (b) PDM gate signals to S1 and S2 (2V/div, 50μs/div) (c) Output voltage at 10% DPDM (40V/div,50μs/div) (d) Output current at 10% DPDM (2A/div,25μs)

The operation of the inverter circuit under a 32 kHz operating frequency with a increased load of 500W has been performed. The corresponding hardware results of the gate pulses and the output voltage are shown in Figs. 14(a) and 14(b), respectively. Fig. 14(c) shows the transition of the output from the zero power period to the power injection period. The transient period for the rise in the output voltage of the inverter can be seen better in Fig. 14(d). It takes 20ns to get settled to the steady state value. The voltage across switch S1 (Vs1) and the current through switch S1 (Is1) during the turning off condition are shown in Fig. 14(e). It can be observed from the waveform that the switches undergo the ZVS condition at the turn off instant.

Fig. 14.(a) Gate pulses to the switches S1and the output voltage (32kHz with DPDM of 50%) (5V/div,50V/div,100μs/div). (b) Output voltage of the inverter with 32kHz frequency (40V/div,100μs/div). (c) Zoomed view of the output voltage shown in (20V/div,10μs/div). (d) Transient period for the rise in output voltage shown in (5V/div,1μs/div). (e) Voltage across the switch S1 (Vs1) and Current through the switch S1 (Is1) (20V/div,5A/div,10μs/div).

Under the fixed frequency operating condition, the presented VDC PDM control ensures a wide power variation with a variation of the control variable DPDM as shown in Fig. 15(a). There is a linear relationship between DPDM and the output power. The variation of the inverter module losses for different values of the input power is shown in Fig. 15(b). With a constant switching frequency, the soft switching condition is maintained at different values of the load power. Since the ZVS condition is maintained in the proposed technique, the inverter losses are reduced when compared to the PWM method. For different input powers, the output power of the conventional PWM and the proposed VDC PDM control are compared in Fig. 15(c). It can be observed that the proposed control scheme improves the output power more than conventional one due to the reduction in switching losses.

Fig. 15.(a) Variation of output power for different values of DPDM. (b) Variation of inverter module losses for different values of input power. (c) Variation of output power for different values of input power.

The claims of the proposed study compared to the studies discussed in other papers are as follows: 1. The proposed study analyzes the PLL based VDC PDM control for the widely used half bridge inverter circuit. This paper compares the conventional PLL based PWM and the PDM control logic with respect to losses and output power. 2. In the hardware, the DPDM control signal is generated by a PIC microcontroller. The transient time taken by the control circuit to lock the resonant frequency at start-up duration is less due to the use of the microcontroller. When the locking time is less, the switching losses are also less during the start-up duration. The cost of the microcontroller is also less. 3. In the proposed study, the PDM control circuit adjusts the output power by varying the PDM duty cycle instead of by varying the PDM switching frequency. i.e. The time period of the low frequency signal (TPDM) is not varied. This avoids the problems due to acoustic noise.

 

V. CONCLUSIONS

This paper presented a PLL based VDC PDM power control scheme in a class-D inverter for an IH load. The design and analysis of the inverter for IH applications are presented. The principle of the proposed control scheme for power control is also discussed in detail. The performance of the proposed control scheme is verified through simulation results. Experimental verification of the VDC PDM scheme is also done with a prototype module. From the simulation and experimental results it can be concluded that the control scheme has the following advantages: a simple configuration, a wide load power control range, reduced switching losses and high efficiency when compared to the conventional PWM scheme. The ZVS operating condition is guaranteed in the load range of 10% to 100%. It has been observed that with a DPDM below 10%, the load current is pulsating and causes the NON-ZVS condition.