• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1643-1647
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• 2003

This paper, we propose a new high noise immunity phase-locked loop(PLL) which can suppress the high incident noise coupling with large amplitude and long period to the input frequency of PLL and keeps constant frequency and phase of the VCO output for providing the high stability distribution clock pulse.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.262-264
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• 1996

This paper presents a new dual loop control using novel vector phase locked loop(VP-PLL) for a high power static var compensator(SVC) with three-level GTO voltage source inverter(VSI). Through circuit DQ-transformation, a simple dq-axis equivalent circuit is obtained. From this, DC analysis is carried out to obtain maximum controllable phase angle ${\alpha}_{max}$ per unit current between the three phase source and the switching function of inverter, and AC open-loop transfer function is given. Because ${\alpha}_{max}$ becomes small in high power SVC, this paper proposes VP-PLL for more accurate $\alpha$-control. As a result, the overall control loop has dual loop structure, which consists of inner VP-PLL for synchronizing the phase angle with source and outer Q-loop for compensating reactive power of load. Finally, the validity of the proposed control method is verified through the experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.134-141
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• 2009

The new method is proposed to improve the dynamics of the phase angle detector during abrupt voltage dip caused by a grid fault. Usually, LPF(low pass filter) is used in the feedback loop of SRF(Synchronous Reference Frame) - PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. A better transient response can be obtained with the proposed design method for SRF-PLL by the analysis of linearized model of the PLL system including LPF. Furthermore, in the proposed method, the controller gain and LPF cut-off frequency are changed from normal value to transient value when the voltage disturbance is detected. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the experiment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1132-1135
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• 2002

In this paper, we propose a phase-locked loop (PLL) with dual loops in which advantages of both loops can be combined. Frequency-locked loop (FLL) which is composed of two frequency-to-voltage converters (FVC) and an amplifier makes the frequency synchronize very fast and output signal is synchronized in phase with the input reference signal by charge pump PLL. This structure can improve the trade-off between acquisition behavior and locked behavior.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.145-151
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• 2008

This paper proposes the PLL method using positive sequence voltage which is estimated by full-order state observer to find an accurate phase angle under the condition of unbalanced utility voltage. The proposed method uses the full-order state observer instead of existing method(APF All Pass Filter) to find a positive sequence of a utility voltage and this proposed method improves transient response of an estimated phase angle when a three-phase utility voltage becomes unbalanced. To compare proposed method withexisting method, experiments have been done for a phase angle detection of utility voltage when a three-phase utility voltage becomes unbalanced. Their results show that transient state response of proposed method is improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2444-2450
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• 2011

In this paper, we propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). The fractional spurs are suppressed by using a new PFD. The new PFD architecture with two different edge detection methods is used to suppress the fractional spur by limiting a maximum width of the output signals of PFD. The proposed PLL was simulated by HSPICE using a 0.35m CMOS parameters. The simulation results show that the proposed PLL is able to suppress fractional spurs with fast locking.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.53-59
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• 2000

A received signal in mobile communication environments exhibits variation in both amplitude and phase due to the multipath fading. Therefore we analyzed the performance of DS/CDMA(Direct Sequence/code Division Multiple Access) DPSK(Differential Phase Shift Keying) system for the variations of PLL(Phase Locked Loop) gain with Tikhonov probability density function, assuming that the phase difference between transmitter and receiver signals is phase error. As a result, it is discovered that the performance of system could be improved by the control of PLL gain in compared with the DPSK system which does not consider the phase error. If the PLL gain is 1dB, the difference of two systems is 4.8dB and 0.4dB at 7dB. and if 30dB, it coincides. From above, it

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.3
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• pp.20-25
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• 1975

A microwave oscillator stabilized by a phase-locked loop (PLL) is developed. The PLL system is chosen 'compared with the cavity stabilized oscillator in view of the domestic manufacturing, because special machining and materials are needed for the latter. A sampler with a low pass filter is shown to be used as a phase detector in the PLL, and the sampler capable of sampling up to 4GHz is developed for this use. Frequency stability of about 10-6 is obtained from the developed microwave oscillator, operating at 2.16 GHz with more than 120 milliwatts output power, Ivhereby a crystal oscillator operating at about 110MHz is used as a reference source in the PLL. The capturing range of this oscillator is extended up to its lock-in-range of about 10MHz by employing a search oscillator in the system.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.368-371
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• 2000

The PLL(Phase-Locked Loop) techniques re employed to make the switching frequency of a resonant inverter follow the resonant frequency which may vary due to the load variations during operation. The conventional design guide of PLL is not suitable in these case since the inverter characteristics are not considered. In this paper the phase characteristics of a resonant inverter is analysed and added to the closed loop. And the design of PLL with digital phase detector is illustrated for the output frequency to track the resonant frequency of the inverter.