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http://dx.doi.org/10.6109/jkiice.2011.15.11.2444

A Fractional-N Phase Locked Loop with Multiple Phase Frequency Detector  

Choi, Young-Shig (부경대학교)
Choi, Hyek-Hwan (부경대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.15, no.11, 2011 , pp. 2444-2450 More about this Journal
Abstract
In this paper, we propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). The fractional spurs are suppressed by using a new PFD. The new PFD architecture with two different edge detection methods is used to suppress the fractional spur by limiting a maximum width of the output signals of PFD. The proposed PLL was simulated by HSPICE using a 0.35m CMOS parameters. The simulation results show that the proposed PLL is able to suppress fractional spurs with fast locking.
Keywords
Phase locked loop (PLL); PFD; ${\Sigma}{\Delta}$ fractional-N; fractional spur;
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