• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• Journal of Power Electronics
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• v.17 no.1
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• pp.262-271
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• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.85.1-85
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• 2001

A phase lock loop (PLL) circuit is a wellknown electronic circuit in communication engineering and other areas. In this paper, we present application of the PLL and fuzzy logic for DC motor control which are mixed well to be more effective for motor control. With this scheme, the control system can reach the set point rapidly, especially, it can eliminate noises. In addition, the PLL makes the system to have more stability; whereas, fuzzy logic controls helping PLL to be able to lock rapidly for a good response. The experiment result shows that the proposed control system works more efficacious. By performance comparison between the pure PLL control and the hybrid architecture of PLL with the fuzzy control, the result reveals the hybrid control ...

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.206-212
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• 2008

This paper proposes the PLL(Phase-Locked Loop) algorithm by a new FFT(Fast Fourier Transform) in a grid-connected PV PCS(Photovoltaics Power Conditionning System). The grid-connected inverter that is applied in a new renewable energy field needs the grid phase information for synchronism. Unlike the PLL which is normally used by three phase D-Q conversion, the preposed PLL algorithm using FFT has non-gain tuning and the powerful noise elimination by the characteristics of FFT. Both simulation and experimental result show that proposed algorithm has the good capacity.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.394-396
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• 2007

Radio occultation (RO) technique has been used in planetary science since 1960s. When signal goes through atmosphere, it is refracted due to the gradient of atmospheric refractivity. In 1995, the first low earth orbit (LEO) satellite, MicroLab-1, was launched to conduct RO mission. It receives the signal from global positioning system (GPS) satellites. After MicroLab-1, other RO missions, such as CHAMP, SAC-C, and GRACE, are executed in several years later. In 2006, Taiwan launched six LEO satellites for RO mission. The mission name is Constellation Observing System for Meteorology, Ionosphere and Climate (COSMIC). Under some abnormal situations, multipath and strong fluctuation in phase and amplitude of the signal appear in moist troposphere. Therefore, open loop (OL) technique has been applied to replace traditional phase lock loop (PLL) technique. In this paper, we will summarize the retrieval processing procedure and discuss the advantages and disadvantages of OL technique.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.903-911
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• 2014

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.