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http://dx.doi.org/10.6109/JKIICE.2009.13.11.2378

Design of a Sub-micron Locking Time Integer-N PLL Using a Delay Locked-Loop  

Choi, Hyek-Hwan (국립부경대학교)
Kwon, Tae-Ha (국립부경대학교)
Abstract
A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.
Keywords
PLL; Fast Locking; adaptive bandwidth;
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