• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.4
• /
• pp.97-102
• /
• 2007

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is implementation of a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• Journal of Power Electronics
• /
• v.17 no.6
• /
• pp.1600-1610
• /
• 2017

We propose maximum power extraction from a rooftop solar photovoltaic (PV) array during partial shading conditions. Partial shading is unavoidable during power extraction from rooftop PV systems due to nearby tall buildings (construction of additional floors) and trees (growth of trees). Many reconfiguration techniques can be used to extract maximum power in partial shading conditions, but in several cases, the real maximum power output is not achieved. In this study, a new switched PV technique is proposed to enhance the power output. The proposed technique is simple to use and more cost effective than other reconfiguration techniques. Therefore, it is suitable for rooftop applications. The power output of the proposed technique is compared with that of existing techniques with similar shading patterns. Eight panels with ratings of 250 watts (2 kW) each are used for testing. MATLAB simulation and hardware verification are done for the proposed and existing techniques. The proposed technique is implemented on a $4{\times}2$ PV array, although it can be extended to a number of arrays.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.531-532
• /
• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.18 no.1
• /
• pp.21-31
• /
• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.

• Proceedings of the IEEK Conference
• /
• 2003.07a
• /
• pp.422-425
• /
• 2003

Software reconfigurable radio will give future users a number of benefits like global roaming, multi mode, multi band, and multi standard. It will also offer complete programmability and reconfigurability to both multi mode and multi functional communication terminal and network nodes. This configuration will be implemented by application of different combination of radio configurable software. In this paper, It proposes the algorithm needed for reconfiguration with basic explanation of the software download. A description of an implementation such reconfiguration processes as partial download and full download and critical and non-critical download installation using the registration table in included.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.571-572
• /
• 2006

A simulation tool for design space exploration of a real-time reconfiguration system was developed in this paper. We described an algorithm for a partial real-time reconfiguration to utilize already existing configured functional units and applied it to H.263 encoder application. This scheme allows us to find a starting configuration for the further optimization without actually building a prototype.

• Nuclear Engineering and Technology
• /
• v.54 no.6
• /
• pp.2031-2036
• /
• 2022

Energetic particle strikes the device and induces data corruption in the configuration memory (CRAM), causing errors and even malfunctions in a system on chip (SoC). Software-based fault injection is a convenient way to assess device performance. In this paper, dynamic partial reconfiguration (DPR) is adopted to make fault injection on a Xilinx 16 nm FinFET Ultrascale+ MPSoC. And the reconfiguration module implements the Sobel and Gaussian image filtering, respectively. Fault injections are executed on the static and reconfiguration modules' bitstreams, respectively. Another contribution is that the failure modes and effects analysis (FMEA) method is applied to evaluate the system reliability, according to the obtained injection results. This paper proposes a software-based solution to estimate programmable device vulnerability.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.925-933
• /
• 2019

In this paper, we implement ZYNQ SoC-based post-processing system that utilizes partial reconfiguration to remove blocking artifacts generated by compression algorithm. Hardware implementation of the deblocking filter in a Field Programmable Gate Array (FPGA) provides high computational capability and can be partially reconfigured to process 1080p images in real time. Partially reconfigurable areas in FPGA can be utilized to use hardware more efficiently in highly resource-constrained embedded systems. Experimental results of the proposed system show improvement of visual quality both objectively and subjectively with 0.6dB higher PSNR after deblocking filtering process. The measured power consumption of the deblocking filter during run-time is 68.33mW.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.12
• /
• pp.1688-1696
• /
• 2020

The paradigm of Internet-of-things(IoT) systems is changing from a cloud-based system to an edge-based system to solve delays caused by network congestion, server overload and security issues due to data transmission. However, edge-based IoT systems have fatal weaknesses such as lack of performance and flexibility due to various limitations. To improve performance, application-specific hardware can be implemented in the edge device, but performance cannot be improved except for specific applications due to a fixed function. This paper introduces a edge-centric metamorphic IoT(mIoT) platform that can use a variety of hardware through on-demand partial reconfiguration despite the limited hardware resources of the edge device, so we can increase the performance and flexibility of the edge device. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to previous studies in which the reconfiguration algorithm was executed on the server.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.10a
• /
• pp.655-658
• /
• 2016

Xilinx 7-Series FPGA(Field Programmable Gate Array)s mainly used for the implementation of high-performance digital circuit have SRAM-type configuration memory and can malfunction when soft errors occur in their configuration memory. SEM(Soft Error Mitigation Controller) offered by Xilinx helps users mitigate the influence of soft errors in configuration memory. When soft errors occur, SEM Controller can recover the state of FPGA through partial reconfiguration if the soft errors are correctable by ECC(Error Correction Code) and CRC(Cyclic Redundancy Code). This paper presents the availability analysis of Xilinx 7-Series FPGAs against soft errors under the protection of the SEM Controller. Availability functions are derived and compared according to the correction capability of the SEM Controller. The result may help to estimate the reliability of SRAM-based FPGA running in an environment where soft errors may occur.