• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.119-120
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• 2006

The impedance spectroscopy is one of the effective ways to understand the electrical properties of organic light emitting diodes. The frequency-dependant properties of small molecule based OLEDs have been studied. The equivalent circuit of single-layer device is composed of contact resistance ($R_c$), bulk resistance ($R_p$) and bulk capacitance ($C_p$). The equivalent circuit of double layer device is composed of two parallel circuits connected in series, each of which is a parallel resistor and a capacitor. We have fabricated a double layer device indium-rio-oxide (ITO, anode), N,NV -diphenyl- N,NV -bis(3-methylphenyI)-1,1V -diphenyl-4,4V-diamine (TPD, hole-transporting layer), tris-(8-hydroxyquinoline) aluminum (Alq3, emitting layer), and aluminum (AI, cathode) and two single layer devices ([TO/ Alq3/ AI, ITO/TPD/AI).

• Journal of Power Electronics
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• v.12 no.6
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• pp.869-877
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• 2012

This paper presents a current-balancing circuit for security lights that uses parallel-connected LEDs. The parallel connection of LEDs causes current differences between the LED strings because of characteristic deviations. These differences can reduce the lifespan of a particular point of LEDs by thermal spotting. They can also cause non-uniform luminance of the lighting device. Among the different methods for solving these problems, the method using current-balancing transformers makes it easy to compensate for current differences and it has a simple circuitry. However, while the balancing transformer has been applied to AC light sources, LEDs operate on a DC source, so the driving circuitry and the design method have to be changed and their performances must be verified. Thus in this paper, a design method of the balancing transformer network and the driving circuitry for LEDs is proposed. The proposed design method could have a smaller size than the conventional design method. The proposed circuitry is applied to three types of 100-watt LED security lights, which use different LEDs. Experimental results are presented to verify the performance of the designed driving circuits.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.5
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• pp.365-371
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• 2019

This study shows the feasibility of the parameter of the 1st RC parallel equivalent circuit as a factor of the heat generation of lithium-ion cell. The internal resistance of a lithium-ion cell consists of ohmic and polarization resistances. The internal resistances at various SOCs of the lithium-ion cell are obtained via an electrical characteristic test. The internal resistance is inversely obtained through the amount of heat generated during the experiment. By comparing the resistances obtained using the two methods, the summation of ohmic and polarization resistances is identified as the heating factor of lithium-ion battery. Finally, the amounts of heat generated from the 2C, 3C, and 4C-rate discharge experiments and the COMSOL multiphysics simulation using the summation of ohmic and polarization resistances as the heating parameter are compared. The comparison shows the feasibility of the electrical parameters of the 1st RC parallel equivalent circuit as the heating factor.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.153-160
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• 2019

This study proposes a current source-type pulse generator to improve output voltage and current waveforms under a capacitively coupled plasma (CCP) system. The proposed circuit comprises two parallel-connected current source-type converters. These converters can satisfy the required output waveforms of plasma processing. The parallel-connected converters operate without reverse current fault by applying a time-delay control technique. Conventional voltage source converters based on pulse power supply exhibit drawbacks in short-circuit current, and problems occur when they are applied to a CCP system. The proposed pulse power supply based on a current source converter fundamentally solves the short-circuit current problem. Therefore, this topology can improve the voltage and current accuracy of a CCP system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.48-55
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• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

• The KIPS Transactions:PartA
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• v.15A no.2
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• pp.69-74
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• 2008

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.20-29
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• 1998

This paper proposes the algorithms that design the highly parallel multiple-valued logic curcuit and assign the code to each node of DCG(Directed Cyclic Graph) of length 1. The conventional Nakajima's algorithm have some problems, so this paper introduce the matrix equation from DCG of length 1 and proposes circuit design algorithms according to the DCG of length 1. Using the proposed circuit design algorithms in this paper, it become realized that was not able to design from Nakajima's algorithm. Also, making a comparision between the circuit design using Nakajima's algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed curcuit design algorithm in this paper, it is possible to design curcuit that DCG have natural number, so it have the following advantages; reduction of the curcuit input/output digits, simplification of curcuit composition, reduction of computation time and cost. And we show compatibility and verification about this paper's algorithm.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.299-304
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• 2020

This paper proposes the design of circular sector shaped power divider-combiner with a planar structure. This structure can be constructed in series, and due to the circular sector shape, it is possible to simplify circuit configuration and improve the amplitude and phase balanced characteristics of the output. It has a simple input matching circuit and an RC parallel circuit was inserted between the output ports to improve the reflection coefficient and isolation of the output. Since the designed divider-combiner are structurally designed in a symmetrical shape of a sector, even if the output ports are composed of two or four output ports, they have excellent characteristics with an amplitude balance of ± 0.1 dB and a phase balance of ± 1o between outputs. To prove these characteristics, it was confirmed that the characteristics of the planar power divider-combiner fabricated at an operating frequency of 2 GHz are in good agreement with the simulation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1489-1496
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• 2010

A feed forward differential architecture of analog PRML decoder is investigated to implement on analog parallel processing circuits. The conventional PRML decoder performs the trellis processing with the implementation of single stage in digital and its repeated use. The analog parallel processing-based PRML comes from the idea that the decoding of PRML is done mainly with the information of the first several number of stages. Shortening the trellis processing stages but implementing it with analog parallel circuits, several benefits including higher speed, no memory requirement and no A/D converter requirement are obtained. Most of the conventional analog parallel processing-based PRML decoders are differential architecture with the feedback of the previous decoded data. The architecture used in this paper is without feedback, where error metric accumulation is allowed to start from all the states of the decoding stage, which enables to be decoded without feedback. The circuit of the proposed architecture is simpler than that of the conventional analog parallel processing structure with the similar decoding performance. Characteristics of the feed forward differential architecture are investigated through various simulation studies.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.