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http://dx.doi.org/10.5392/JKCA.2016.16.03.091

Design of High-performance Parallel BCH Decoder for Error Collection in MLC Flash Memory  

Choi, Won-Jung (강원대학교 공학대학 전자정보통신공학과)
Lee, Je-Hoon (강원대학교 공학대학 전자정보통신공학부)
Sung, Won-Ki (강원대학교 공학대학 전자정보통신공학부)
Publication Information
The Journal of the Korea Contents Association / v.16, no.3, 2016 , pp. 91-101 More about this Journal
Abstract
This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.
Keywords
Error Correction; BCH Code; Parallel Processing; Syndrome Generator;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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