• 전자공학회논문지SC
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• 제45권6호
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• pp.141-148
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• 2008

신재생 에너지 분야에서 각광받고 있는 계통 연계형 태양광 인버터에서는 계통과의 연계를 위해서 반드시 계통의 위상 정보가 필요하다. 본 논문에서는 계통 연계형 태양광 발전 시스템에서의 위상 동기화 방법으로 원하는 기준 신호의 주파수를 구하여 동기신호로 사용하고, DFT(Discrete Fourier Transform) 알고리즘을 이용하여 기준 신호와의 위상차를 구하여 위상차만큼 보상하는 PLL(Phase Locked Loop)의 순시 추종방법을 제안하였다. 또한 DFT 연산에 사용되는 한주기 값들을 샘플링 할때마다 보정 위상 값을 구하는 방법과 특정 주파수의 기준신호에 대한 주파수 및 위상 추종뿐만 아니라 다양한 주파수 신호에 대한 주파수 및 위상을 추종하는 방법을 적용하여 시뮬레이션과 실험을 통해 본 논문의 타당성을 검증하여 유효성을 보이고자 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.742-744
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• 1999

In this paper, a new precharge type PFD for fast locking time of PLL is suggested. It is realized by inserting NMOS transistor and inverter into the precharge part of PFD for isolating the reset of the Up signal from the feedback signal. The new precharge type PFD generates the Up signal while the feedback signal is fixed at a high level. Therefore the new PFD output is increased than the conventional precharge type PFD output. As a result of the increased PFD output, fast locking of PLLs is achieved. Additionally, with control the falling time of the inverter, the dead-zone is reduced and the jitter characteristics are improved. The whole characteristics of PFD and PLL are simulated by using HSPICE. Simulation results show that the dead-zone is 20ps and the locking time of PLL using the new PFD is 38ns at the 350MHz frequency of referecne signal. This value is quite small compared with conventional PFD.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.116-119
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• 2005

In this paper, we propose the PLL system of the local oscillator system for the millimeter wave band's radio astronomy receiving system. The development of the proposed local oscillator system based on the YIG oscillator VCO with 26.5 ${\sim}$ 40GHz specification. This system consists of the oscillator part including the YIG VCO, the harmonic mixer, and the isolator, the RF processing part including the triplexer, limiter, and RF discrimination processor. and the PLL system including YIG modulator and controller. Based on this configuration. we verify the frequency and power stability of the developed local oscillator system according to some temperature variation. From this test results we confirm the stable output frequency and power characteristic performance of the developed La system at constant temperature.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• ETRI Journal
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• 제34권2호
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• pp.175-183
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• 2012

Conventional synchronization algorithms for impulse radio require high-speed sampling and a precise local clock. Here, a phase-locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one-tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high-speed ultra-wideband transceiver shows its feasibility, low complexity, and high precision.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.607-608
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• 2006

A CMOS phase-locked loop (PLL) which synthesizes frequencies between $6.336{\sim}8.976GHz$ in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in multi-band orthogonal frequency division multiplexing (OFDM) because frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at 9GHz and 528MHz is integrated and shows the band hopping lower than 1ns.

• 한국전자파학회논문지
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• 제22권2호
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• pp.258-264
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• 2011

본 논문은 GSM(Global System for Mobile communications)에서 주로 사용되는 Offset-PLL(Phase Locked Loop) 방식을 사용하여 낮은 위상 잡음과 빠른 위상 고정 시간, 우수한 불요파 특성을 갖는 주파수 합성기를 설계 제작하였다. 제안된 주파수 합성기의 구조는 3번의 주파수 하향 변환을 통해 낮은 위상 잡음 갖도록 하였으며, 높은 주파수 해상도를 갖도록 세 개의 offset 주파수중 최종 offset 주파수를 DDS(Direct Digital Synthesizer)를 이용하여 생성하였다. 또한, 빠른 스위칭 속도를 가질 수 있도록 DAC(Digital to Analog Converter)를 사용하였다. DAC 사용에 따른 위상 잡음 열화를 줄이기 위해 DAC 노이즈 제거를 위한 필터를 설계하여 성능을 개선하였다.

• 한국전자파학회논문지
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• 제23권11호
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• pp.1280-1287
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• 2012

3.2~6.5 GHz 광대역 특성을 갖는 YTO(YIG Tuned Oscillator) 모듈을 설계 및 제작하였다. 위상 잡음 특성을 개선하기 위해 샘플링 믹서를 이용한 offset PLL(Phase Locked Loop) 구조로 설계하였다. 이 방식은 샘플링 믹서, 위상 비교기, 루프 필터, 전류 드라이버 회로, YTO로 구성된다. 측정 결과, 4.5 GHz에서 위상 잡음은 수식으로 도출한 값과 유사한 10 kHz offset 주파수에서 -100 dBc/Hz를 얻었다. 제작된 YTO 모듈의 위상 잡음은 동작 주파수 대역에서 기존 PLL 구조에 비해 10 dB 이상 우수함을 확인하였다.

• 조명전기설비학회논문지
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• 제28권11호
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• pp.68-76
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• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.

• Biotechnology and Bioprocess Engineering:BBE
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• 제9권3호
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• pp.179-183
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• 2004

A biocompatible polyelectrolyte complex multilayer (PECML) film consisting of poly-L-lysine (PLL) as a polycation and hyaluronic acid (HA) as a polyanion was developed to test its use for surface modification to prevent cell attachment and protein drug delivery. The formation of PECML through the electrostatic interaction of HA and PLL was confirmed by contact angle measurement, ESCA analysis, and HA content analysis. HA content increased rapidly up to 8 cycles for HA/PLL deposition and then slightly increased with an increasing number of deposition cycle. In vitro release of PLL in the PECML continued up to 4 days and ca. 25% of HA remained on the chitosan-coated cover glass after in vitro release test for 7 days. From the results, PECML of HA and PLL appeared to be stable for about 4 days. The surface modification of the chitosan-coated cover glass with PECML resulted in drastically reduced peripheral blood mononuclear cell (PBMC) attachment. Concerned with its use for protein drug delivery, we confirmed that bovine serum albumin (BSA) as a model protein could be incorporated into the PECML and its release might be triggered by the degradation of HA with hyaluronidase.