• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1108-1113
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• 1992

In this paper, the high frequency twin resonant inverter using MOSFET is presented. The output control is excellent and the EMI noise is reduced, because the output appear as the vector sum of current in each unit inverter. The output voltage and the output current of the inverter are controlled by PLL. In this paper, the principle of the twin resonant method is described. And computer simulations and experimental results are shown.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1161-1164
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• 1992

In this paper demonstrates the possibiity of utilising clamped mode - series resonant converter technology in the high frequency link inverter configuration. Main circuit of the proposed inverter is analyzed through circuit analys and waveform simulation. In control circuit PLL circuit and 8 bit single chip microcontroller is adopted, therefore flexibility and accuracy of control circuit is increased.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.19 no.4
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• pp.6-11
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• 2011

Launch of the first Quasi-Zentih Satellite System (QZSS) satellite, dubbed Michibiki, took place September 11, 2010 and technical and application verification of the satellite is being carried out. This paper presents the results obtained from processing of the L5 signal transmitted from the QZSS satellite. The QZSS L5 signal is collected in ETRI, Korea. And then, the acquisition and tracking are performed by the L5 software receiver implemented by ETRI. The tracking loop of FLL, PLL, and DLL, the EPL correlator output, and the C/No output results show that the QZSS L5 signal is normally processed. Finally, the paper demonstrates that the QZSS L5 signal could be used as GPS satellite based augmentation system in Korea as well as Japan.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.62-65
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• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.275-278
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• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• Journal of Power Electronics
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• v.12 no.4
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• pp.604-614
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• 2012

This paper presents a comparative study of position sensorless control schemes based on back-electromotive force (back-EMF) estimation in permanent magnet synchronous motors (PMSM). The characteristics of the estimated back-EMF signals are analyzed using various mathematical models of a PMSM. The transfer functions of the estimators, based on the extended EMF model in the rotor reference frame, are derived to show their similarity. They are then used for the analysis of the effects of both the motor parameter variations and the voltage errors due to inverter nonlinearity on the accuracy of the back-EMF estimation. The differences between a phase-locked-loop (PLL) type estimator and a Luenberger observer type estimator, generally used for extracting rotor speed and position information from estimated back-EMF signals, are also examined. An experimental study with a 250-W interior-permanent-magnet machine has been performed to validate the analyses.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.476-478
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• 2006

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a $0.25{\mu}m$ CMOS process. In the design a new dynamic D-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates up to 2.5GHz and consumes 3.1mA at 2.5GHz operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.198-201
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• 2014

The phase frequency detector (PFD) is one of the most important building blocks of a phase locked Loop (PLL). Due to blind-zone problem, the detection range of the PFD is low. The blind zone of a PFD directly depends upon the reset time of the PFD and the pre-charge time of the internal nodes of the PFD. Taking these two parameters into consideration, a PFD is designed to achieve a small blind zone closer to the limit imposed by process-voltage-temperature variations. In this paper an enhanced architecture is proposed for dynamic logic PFD to minimize the blind-zone problem. The techniques used are inverter sizing, transistor reordering and use of pre-charge transistors. The PFD is implemented in 180 nm technology with supply voltage of 1.8 V.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.28-34
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• 1986

The frequency synthesizer for Fast Frequency Hopping System musy be capable of a fast tuning with a small step frequency over wide band. The most conventional frequency synthesizer that uses the phase locked loop (PLL) enables the wide band problem but have a poor side of the low resolution and the transient response. In this paper, we have discussed the experimental results of a direct digital frequency synthesizer which can be applicable to the Fast Frequency Hopping System, using digital-to-analoq (D/A)conversion techniques. With this system we can find the merits of a fine resolution and the possibility of a fast tuning leaving the problems of transent frequency.