• 센서학회지
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• 제23권5호
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• pp.337-341
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• 2014

For various additives doped-$VO_2$ critical temperature sensors using the nature of semiconductor to metal transition, the crystallinity, microstructure, and temperature vs. resistance characteristics were systematically investigated. As a starting material of $VO_2$ sensor, vanadium pentoxide ($V_2O_5$) powders were used, and CaO, SrO, $Bi_2O_3$, $TiO_2$, and PbO dopants were used, respectively. The $V_2O_5$ powders with dopants were mixed with a vehicle to form paste. This paste was silk screen-printed on $Al_2O_3$ substrates and then $V_2O_5$-based thick films were heat-treated at $500^{\circ}C$ for 2 hours in $N_2$ gas atmosphere for the reduction to $VO_2$. From X-ray diffraction analysis, $VO_2$ phases for pure $VO_2$, and CaO and SrO-doped $VO_2$ thick films were confirmed and their grain sizes were 0.57 to $0.59{\mu}m$. The on/off resistance ratio of the $VO_2$ sensor in phase transition temperature range was $5.3{\times}10^3$ and that of the 0.5 wt.% CaO-doped $VO_2$ sensor was $5.46{\times}10^3$. The presented critical temperature sensors could be commercialized for fire-protection and control systems.

• 한국정보통신학회논문지
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• 제20권4호
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• pp.819-825
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• 2016

본 논문에서는 기존의 위상 고정 루프를 병렬 형태로 이중 루프를 구성하였다. 두 개의 루프를 통해서 전달 특성에 따라 원하는 크기의 대역폭을 만든다. 대역 폭의 형태는 동작하는 주파수 대역에서 잡음을 최소화 할 수 있는 위상 고정 루프를 설계하였다. 제안한 위상고정루프는 두 가지 필터를 제어하기 위하여 두 개의 기울기 값을 가지는 전압제어 발진기를 사용하였다. 또한 정확한 위상 고정을 위하여 위상 고정 상태 표시기를 사용하였다. 전체적인 위상 고정 루프가 안정적인 동작하기 위하여 각 각의 루프가 각각 $58.2^{\circ}$, $49.4^{\circ}$의 위상 여유를 가지고 있으며 두 개의 루프를 합쳤을 때에도 $45^{\circ}$이상의 안정적인 위상 여유를 가지는 것을 확인 할 수 있다. 제안된 위상 고정 루프는 1.8V 0.18um CMOS 공정을 이용하여 설계 되었다. 시뮬레이션 결과는 이중 루프를 가지고 위상고정루프의 구조가 원하는 출력 주파수를 생성하며 안정적으로 동작하는 것을 보여 주었다.

• Journal of Information Display
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• 제9권4호
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• pp.21-29
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• 2008

We studied both the wavelength and intensity dependent photo-responses (photofield-effect) in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs). During the a-IGZO TFT illumination with the wavelength range from $460\sim660$ nm (visible range), the off-state drain current $(I_{DS_off})$ only slightly increased while a large increase was observed for the wavelength below 400 nm. The observed results are consistent with the optical gap of $\sim$3.05eV extracted from the absorption measurement. The a-IGZO TFT properties under monochromatic illumination ($\lambda$=420nm) with different intensity was also investigated and $I_{DS_off}$ was found to increase with the light intensity. Throughout the study, the field-effect mobility $(\mu_{eff})$ is almost unchanged. But due to photo-generated charge trapping, a negative threshold voltage $(V_{th})$ shift is observed. The mathematical analysis of the photofield-effect suggests that a highly efficient UV photocurrent conversion process in TFT off-region takes place. Finally, a-IGZO mid-gap density-of-states (DOS) was extracted and is more than an order of magnitude lower than reported value for hydrogenated amorphous silicon (a-Si:H), which can explain a good switching properties observed for a-IGZO TFTs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.45-49
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• 2001

We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.172-173
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• 2006

Metal-ferroelectric-insulator-semiconductor (MFIS) structures with $Bi_{3.35}La_{0.75}Ti_3O_{12}$ (BLT) ferroelectric film and Zirconium oxide ($ZrO_2$) layer were fabricated on p-type Si(100). $ZrO_2$ and BLT films were prepared by sol-gel technique. Surface morphologies of $ZrO_2$ and BLT film were measured by atomic force microscope (AFM). The electrical characteristics of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si film were investigated by C-V and I-V measurements. No hysteretic characteristics was observed in the C-V curve of the Au/$ZrO_2$/Si structure. The memory window width m C-V curve of the Au/BLT/$ZrO_2$/Si diode was about 1.3 V for a voltage sweep of ${\pm}5$ V. The leakage current of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si structures were about $3{\times}10^{-8}$ A at 30 MV/cm and $3{\times}10^{-8}$ A at 3 MV/cm, respectively.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.34.2-34.2
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• 2011

The demand for Ru has been increasing in the electronic, chemical and semiconductor industry. Chemical mechanical planarization (CMP) is one of the fabrication processes for electrode formation and barrier layer removal. The abrasive particles can be easily contaminated on the top surface during the CMP process. This can induce adverse effects on subsequent patterning and film deposition processes. In this study, a post Ru CMP cleaning solution was formulated by using sodium periodate as an etchant and citric acid to modify the zeta potential of alumina particles and Ru surfaces. Ru film (150 nm thickness) was deposited on tetraethylorthosilicate (TEOS) films by the atomic layer deposition method. Ru wafers were cut into $2.0{\times}2.0$ cm pieces for the surface analysis and used for estimating PRE. A laser zeta potential analyzer (LEZA-600, Otsuka Electronics Co., Japan) was used to obtain the zeta potentials of alumina particles and the Ru surface. A contact angle analyzer (Phoenix 300, SEO, Korea) was used to measure the contact angle of the Ru surface. The adhesion force between an alumina particle and Ru wafer surface was measured by an atomic force microscope (AFM, XE-100, Park Systems, Korea). In a solution with citric acid, the zeta potential of the alumina surface was changed to a negative value due to the adsorption of negative citrate ions. However, the hydrous Ru oxide, which has positive surface charge, could be formed on Ru surface in citric acid solution at pH 6 and 8. At pH 6 and 8, relatively low particle removal efficiency was observed in citric acid solution due to the attractive force between the Ru surface and particles. At pH 10, the lowest adhesion force and highest cleaning efficiency were measured due to the repulsive force between the contaminated alumina particle and the Ru surface. The highest PRE was achieved in citric acid solution with NaIO4 below 0.01 M at pH 10.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• 한국재료학회지
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• 제23권8호
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• pp.430-434
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• 2013

Quantum dots(QDs) with their tunable luminescence properties are uniquely suited for use as lumophores in light emitting device. We investigate the microstructural effect on the electroluminescence(EL). Here we report the use of inorganic semiconductors as robust charge transport layers, and demonstrate devices with light emission. We chose mechanically smooth and compositionally amorphous films to prevent electrical shorts. We grew semiconducting oxide films with low free-carrier concentrations to minimize quenching of the QD EL. The hole transport layer(HTL) and electron transport layer(ETL) were chosen to have carrier concentrations and energy-band offsets similar to the QDs so that electron and hole injection into the QD layer was balanced. For the ETL and the HTL, we selected a 40-nm-thick $ZnSnO_x$ with a resistivity of $10{\Omega}{\cdot}cm$, which show bright and uniform emission at a 10 V applied bias. Light emitting uniformity was improved by reducing the rpm of QD spin coating.At a QD concentration of 15.0 mg/mL, we observed bright and uniform electroluminescence at a 12 V applied bias. The significant decrease in QD luminescence can be attributed to the non-uniform QD layers. This suggests that we should control the interface between QD layers and charge transport layers to improve the electroluminescence.

• 한국항공우주학회지
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• 제42권11호
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• pp.981-987
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• 2014

DC/DC 컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 효율이 높은 전력변환기이다. DC/DC 컨버터는 MOSFET(산화물-반도체 전계 효과 트랜지스터), PWM-IC(펄스폭 변조 집적회로) 제어기, 인덕터, 콘덴서 등으로 구성되어있다. MOSFET는 스위치 기능을 수행하는데 코발트 60 ($^{60}Co$) 저준위 감마발생기를 이용한 TID 실험에서 방사선의 영향으로 문턱전압과 항복전압의 변화와 SEGR 실험에 적용된 5종류의 중이온 입자는 MOSFET의 게이트(gate)에 영향을 주어 게이트가 파괴된다. MOSFET의 TID 실험은 40 Krad 까지 수행하였으며, SEGR 실험은 제어보드를 구현한 후 LET(MeV/mg/$cm^2$)별 cross section($cm^2$)을 연구하는데 있다.

• 전자공학회논문지
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• 제50권7호
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• pp.109-114
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• 2013

전력 MOSFET(산화물-반도체 전위 효과 트랜지스터)는 BLDC 모터와 전력 모듈 등에 광범위하게 사용하고 있다. 기존 전력 MOSFET 구조는 온-저항과 항복전압사이에 절충(tradeoff)이 필요하다. 이러한 절충을 하지 않고 최적화를 하기위해 비균일 초접합 트랜치 MOSFET 를 설계하는데 동일한 항복전압에서 균일 초접합 트랜치 MOSFET보다 낮은 온-저항을 갖도록한다. 이를 위해 드리프트 영역에서 우수한 전기장 분포를 달성하기 위하여 선형구조의 도핑 프로파일을 제안하고, 단위 셀 설계, 도핑농도의 특성분석, 전위분포를 SILVACO TCAD 2D인 Atlas 소자 소프트웨어를 사용하여 시뮬에이션을 수행하였다. 결과로 100V 급 MOSFET에서 비균일 초접합 트랜치 MOSFET가 균일 초접합 트랜치 MOSFET보다 온-저항에서 우수한 특성을 보여주고 있다.