• 대한의용생체공학회:의공학회지
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• 제28권6호
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• pp.756-767
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• 2007

For the combination of phosphor screens having various thicknesses and a photodiode array manufactured by complementary metal-oxide-semiconductor (CMOS) process, we report the observation of image-quality degradation under the irradiation of 45-kVp spectrum x rays. The image quality was assessed in terms of dark pixel signal, dynamic range, modulation-transfer function (MTF), noise-power spectrum (NPS), and detective quantum efficiency (DQE). For the accumulation of the absorbed dose, the radiation-induced increase both in dark signal and noise resulted in the gradual reduction in dynamic range. While the MTF was only slightly affected by the total ionizing dose, the noise power in the case of $Min-R^{TM}$ screen, which is the thinnest one among the considered screens in this study, became larger as the total dose was increased. This is caused by incomplete correction of the dark current fixed-pattern noise. In addition, the increase tendency in NPS was independent of the spatial frequency. For the cascaded model analysis, the additional noise source is from direct absorption of x-ray photons. The change in NPS with respect to the total dose degrades the DQE. However, with carefully updated and applied correction, we can overcome the detrimental effects of increased dark current on NPS and DQE. This study gives an initial motivation that the periodic monitoring of the image-quality degradation is an important issue for the long-term and healthy use of digital x-ray imaging detectors.

• 한국전자통신학회논문지
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• 제12권5호
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• pp.791-796
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• 2017

본 연구에서는 DRAM 커패시터의 유전막 박막화를 위한 Load Lock(L/L) LPCVD 시스템을 이용한 적층형 커패시터의 제조 공정이 셀 커패시턴스에 미치는 영향을 조사하였다. 그 결과 기존의 non-L/L 장치에 비하여 약 $6{\AA}$의 산화막 유효두께를 낮춤으로 커패시턴스로 환산 시 약 3-4 fF의 차이가 나타남을 확인할 수 있었다. 또한 절연막으로써 질화막 두께의 측정 범위가 정상적인 관리 범위의 분포임에도 불구하고 Cs는 계산치보다 약 3~6 fF 정도 낮은 것으로 확인되었다. 이는 node poly FI CD가 spec 상한치로 관리되어 셀 표면적의 감소를 초래하였고 이는 약 2fF의 Cs 저하를 나타내었다. 따라서 안정적인 Cs의 확보를 위해서는 절연막의 두께 및 CD 관리를 spec 중심값의 10 % 이내로 관리할 필요가 있음을 확인하였다.

• 전자공학회논문지
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• 제50권6호
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• pp.131-137
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• 2013

광각 카메라는 단 초점 렌즈를 장착하여 넓은 시야의 이미지를 처리하는데, 렌즈의 광학 문제로 인해 이미지에 베럴 왜곡(barrel distortion)이 발생한다. 본 논문에서는 베럴 왜곡을 실시간 디지털 신호처리를 통해 보정하기 위한 낮은 복잡도의 프로세서 구조를 제시하고 이를 실제 구현하여 유효성을 검증하였다. 제안하는 왜곡 보정 프로세서는 하드웨어 복잡도를 낮추기 위해서, 좌표 위치 보정에 필요한 계산을 점증적(incremental)으로 수행한다. 또한, 높은 보정 속도를 달성하기 위해 파이프 라인 구조로 설계하였다. 설계된 보정 프로세서는 $0.11{\mu}m$ complementary metal-oxide semiconductor(CMOS) 공정을 사용하여 14.3K의 논리 게이트로 구현되었다. $2048{\times}2048$ 픽셀 영상에 대하여, 최대 314MHz의 동작 주파수로 초당 74.86번의 속도로 보정이 가능하다.

• 센서학회지
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• 제27권2호
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• 센서학회지
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• 제29권2호
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• pp.123-127
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• 2020

In this paper, the estimation of the disparity for depth extraction in monochrome complementary metal-oxide-semiconductor (CMOS) image sensors with offset pixel apertures is presented. To obtain the depth information, the disparity information between two different channel data of the offset pixel apertures is required. The disparity is caused by the difference in the response angle between the left- and right-offset pixel aperture images. A depth map is implemented by the generated disparity. Therefore, the disparity is the most important factor for realizing 3D images from the designed CMOS image sensor with offset pixel apertures. The disparity is influenced by the pixel height and offset value of the offset pixel aperture. To confirm this correlation, the offset value is set to maximum within the pixel area, and the disparity values corresponding to the difference in the heights are calculated and compared. The disparity is derived using the camera-lens formula. Two monochrome CMOS image sensors with offset pixel apertures are used in the disparity estimation.

• 한국재료학회지
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• 제3권4호
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• pp.319-326
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• 1993

Hydroxide법으로 ${\alpha}$-주산산(stannic acid)을 만든후, 하고온도를 $500^{\circ}C$~$1100^{\circ}C$로 조정하여 일차입자(Crystallite)크기가 8-54nm인 $SnO_2$ 분말을 제작하였다. 분말의 입자(drystalite)클기에 따른 분말특성와 $H_2$, CO가스(0.5v/o)에 대한 감응성 미치공기중에서의 저상변화특성에 미치는 영향을 조사하였다. 입자크기가 감소함에 따라, 분말의 FTIR 흡습특성은 증가하였으나, 격자상수는 일정하였다. 후막소자에서, $H_2$가스에 대해 최대감도를 나타내는 온도와 공기중에서 최소저항을 나타내는 온도는 입자크기가 미세해짐에 따라 점차 낮아졌다. 최소저항점과 최대감도점의 온도저하를 산소흡착종의 활성화에너지의 감소라고 유추하였고, 이러한 에너지의 감소가 미세입자에 의한 감도향상요인 중의 한가지라고 제의하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.240-250
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• 2010

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

• 태양에너지
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• 제17권2호
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• pp.55-66
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• 1997

CdTe/CdS 태양전지 제작에 필요한 다결정 CdS 박막을 ITO 전도 유리기판위에 SSD법, SPD법 및 CBD법 으로 제작하고 열처리 한 후 그 결정구조와 광학적 특성을 조사하였다. 박막은 모두 Wurtzite 구조를 보였고 SSD법과 CBD법의 박막은 $0.5{\mu}m$ 크기의 CdS 입자가 불규칙적으로 형성되어 증착되어 있음을 보였고, $400^{\circ}C$로 진공중에서 열처리 할 때 입자의 크기가 약간 증가하였다. SPD법의 박막은 (002)방향으로 결정이 성장되고 입자의 크기가 $0.1-0.3{\mu}m$ 이었다. 에너지 밴드갭 및 결함 상태를 광학적 흡수, 광 루미니센스, 라만 및 광 열 편기 스펙트럼(PDS) 측정을 통해 조사하였다.

• 한국전기전자재료학회논문지
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• 제27권6호
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• pp.356-360
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• 2014

In this paper, the effect of underpass structure on quality factor and breakdown voltage of octagonal inductors which were fabricated with 90 nm complementary metal-oxide-semiconductor (CMOS) technology for radio frequency integrated circuit (RFIC) was studied. It was found that quality factor and breakdown voltage of inductors with more than one metal layer for underpass showed improved properties compared to those with one metal layer. However, little change of quality factor and breakdown voltage was observed between the inductors with two and more than two metal layers for underpass. Therefore, underpasses with two metal layers are promising for RFIC designs of the octagonal inductors in 90 nm CMOS technology.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.261-269
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• 2016

A high-performance transmit/receive (T/R) switch is essential for every radio-frequency (RF) device. This paper proposes a T/R switch that is designed in the CEDEC 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology for 2.4 GHz ISM-band RF applications. The switch exhibits a 1 dB insertion loss, a 28.6 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode; meanwhile, for the 1.8 V/0 V control voltages, a 1.1 dB insertion loss and a 19.4 dB isolation were exhibited with an extremely-low power dissipation of 377.14 μW in the receive mode. Besides, the variations of the insertion loss and the isolation of the switch for a temperature change from - 25℃ to 125℃ are 0.019 dB and 0.095 dB, respectively. To obtain a lucrative performance, an active inductor-based resonant circuit, body floating, a transistor W/L optimization, and an isolated CMOS structure were adopted for the switch design. Further, due to the avoidance of bulky inductors and capacitors, a very small chip size of 0.0207 mm² that is the lowest-ever reported chip area for this frequency band was achieved.