• 한국전자통신학회논문지
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• 제4권4호
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• pp.301-305
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• 2009

Pt 나노입자의 합성과 이를 이용한 hybrid Pt-$SiO_2$ 나노입자의 합성을 성공적으로 수행하였으며, self-assembled Pt nanoparticles monolayer를 charge trapping layer로 활용하는 metal-oxide-semiconductor(MOS) type memory의 한 예로 non-volatile memory(NVM)의 응용을 보임으로써 나노입자의 활용 가능성을 보이고, 또한, hybrid Pt-$SiO_2$ 나노입자 박막 층의 제어를 통한 MOS type memory device에의 보다 더 넓은 활용 가능성을 보이고자 하였다.

• Journal of information and communication convergence engineering
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• 제4권1호
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• pp.18-22
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• 2006

A small-sized gas identification system has been fabricated and characterized using an integrated gas sensor array and artificial neural-network. The sensor array consists of four thick-film oxide semiconductor gas sensors whose sensing layers are $In_{2}O_{3}-Sb_{2}O_{5}-Pd-doped\;SnO_2$ + Pd-coated layer, $La_{2}O_{5}-PdCl_{2}-doped\;SnO_2,\;WO_{3}-doped\;SnO_{2}$ + Pt-coated layer and $ThO_{2}-V_{2}O_{5}-PdCl_{2}\;doped\;SnO_{2}$. The small-sized gas identification instrument is composed of a GMS 81504 containing an internal ROM (4k bytes), a RAM (128 bytes) and four-channel AD converter as MPU, LEDs for displaying alarm conditions for three gases (liquefied petroleum gas: LPG, liquefied natural gas: LNG and carbon monoxide: CO) and interface circuits for them. The instrument has been used to identify alarm conditions for three gases among the real circumstances and the identification has been successfully demonstrated.

• ETRI Journal
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• 제42권5호
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• pp.773-780
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• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• 반도체디스플레이기술학회지
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• 제10권3호
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• pp.15-19
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• 2011

The performance of the DRAM is strongly dependent on the purity and surface roughness of the TIT (TiN/Insulator/ TiN) capacitor electrodes. Hence, in the present study, we evaluate the effects of organic contamination and change of surface roughness on the cylindrical TIT capacitor electrodes during the wet cleaning process by various analytical techniques such as TDMS, AFM, XRD and V-SEM. Once the sacrificial oxide and PR (Photo Resist) are removed by HF, the organic contamination and surface oxide films on the bottom Ti/TiN electrode become visible. With prolonged HF process, the surface roughness of the electrode is increased, whereas the amount of oxidized Ti/TiN is reduced due to the HF chemicals. In the 80nm DRAM device fabrication, the organic contamination of the cylindrical TIT capacitor may cause defects like SBD (Storage node Bridge Defect). The SBD fail bit portion is increased as the surface roughness is increased by HF chemicals reactions.

• 한국전기전자재료학회논문지
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• 제29권6호
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• pp.359-364
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• 2016

NiO serves as a window layer for Si photoelectric devices. Due to the wide energy bandgap of NiO, high optical transparency (over 80%) was achieved and applied for Si photoelectric devices. Due to the high the high mobility, the heterojunction device (Al/n-Si/$SiO_2$/p-NiO/ITO) provide ultimately fast photoresponses of rising time of $38.33{\mu}s$ and falling time of $39.25{\mu}s$, respectively. This functional NiO layer would provide benefits for high-performing photoelectric devices, including photodetectors and solar cells.

• 센서학회지
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• 제25권6호
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• pp.423-430
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• 2016

This study used a single metal oxide semiconductor (MOS) sensor to classify the major odorous gases hydrogen sulfide ($H_2S$), ammonia ($NH_3$) and toluene ($C_6H_5CH_3$). In order to classify these odorous substances, the voltage on the MOS sensor heater was gradually reduced in 0.5 V steps 5.0 V to examine the changes to the response by the cooling effect on the sensor as the voltage decreased. The hydrogen sulfide gas showed the highest sensitivity compared to odorless air under approximately 2.5 V and the ammonia and toluene gases showed the highest sensitivity under approximately 5.0 V. In other words, the hydrogen sulfide gas reacted better in the low temperature range of the MOS sensor, and the ammonia and toluene gases reacted better in the high-temperature range. In order to analyze the response characteristics of the MOS sensor by temperature in a pattern, a two-dimensional (2D) x-y pattern analysis was introduced to clearly classify the hydrogen sulfide, ammonia, and toluene gases. The hydrogen sulfide gas was identified by a straight line with a slope of 1.73, whereas the ammonia gas had a slope of 0.05 and the toluene gas had a slope of 0.52. Therefore, the 2D x-y pattern analysis is suggested as a new way to classify these odorous substances.

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.134-137
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• 2019

In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

• 센서학회지
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• 제27권6호
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• 반도체디스플레이기술학회지
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• 제16권4호
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• pp.59-62
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• 2017

In this paper, atmospheric pressure plasma treatment was proposed for high performance indium gallium zinc oxide thin film transistor (IGZO TFT). RF Ar plasma treatment is performed at room temperature under atmospheric pressure as a simple and cost effective channel surface treatment method. The experimental results show that field effect mobility can be enhanced by $2.51cm^2/V{\cdot}s$ from $1.69cm^2/V{\cdot}s$ to $4.20cm^2/V{\cdot}s$ compared with a conventional device without plasma treatment. From X-ray photoelectron spectroscopy (XPS) analysis, the increase of oxygen vacancies and decrease of metal-oxide bonding are observed, which suggests that the suggested atmospheric Ar plasma treatment is a cost-effective useful process method to control the IGZO TFT performance.