• ETRI Journal
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• v.39 no.5
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• pp.737-745
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• 2017

A 6-GHz-to-18-GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a $0.25-{\mu}m$ AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power-added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse-mode condition of a $100-{\mu}s$ pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2139-2149
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• 2016

In this study, a new type of cascaded modular multilevel inverters (CMMLIs) is presented which is able to produce a considerable number of output voltage levels with a reasonable number of components. Accordingly, each series stage of the proposed CMMLI is comprised of two same basic units that are connected with each other through two unidirectional power switches without aiming any of the full H-bridge cells. In addition, since the potentiality for generating a higher number of output voltage levels in CMMLIs hinges on the magnitude of the dc voltage sources used in each series unit, in the rest of this paper, four different algorithms for determining an appropriate value for the dc sources' magnitude are also presented. In the following, a comprehensive topological analysis between some CMMLI structures reported in the literature and proposed structure along with several simulation and experimental results will be also given to validate the lucrative benefits and viability of the proposed topology.

• Journal of Power Electronics
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• v.14 no.4
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• pp.661-670
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• 2014

A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to $V_{in}/2$. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.92-99
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• 2022

Due to space and geographical constraints, the power source may be located outside the island area, resulting in the considerable length of transmission line. In these cases, when an active power is transmitted, unexpected reactive power is generated at a point of common coupling (PCC). Unlike the power transmitted from the power generation source, the reactive power adversely affects the system. This study proposes a new algorithm that controls reactive power at PCC. Causes of reactive power errors are separated into parallel and series components, which allows the algorithm to compensate the reactive current of the inverter output and control reactive power at the PCC through calculations from the impedance, voltage, and current. The proposed algorithm has economic advantages by controlling the reactive power with the inverter of the power source itself, and can flexibly control power against voltage and output variations. Through the simulation, the algorithm was verified by implementing a power source of 3 [kVA] capacity connected to the low voltage system and of 5 [MVA] capacity connected to the extra-high voltage system. Furthermore, a power source of 3 [kVA] capacity inverter is configured and connected to a mock grid, then confirmed through experiments.

• Journal of the Ergonomics Society of Korea
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• v.35 no.5
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• pp.413-423
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• 2016

Objective:The aims of this study are to understand the effects of task (pushing, pulling, and clockwise and counter clockwise twisting) direction on the maximal output and their grip forces and to explore the relationship between the maximal output and the grip forces. Background: Knowing the normative maximal grip force is not enough to design a good hand tool. The industrial designers should understand the required grip forces in various motions toward a specific direction to make an effective and efficient hand tool. Method: Eighteen healthy volunteers participated in the series of isometric maximal output force tests. A custom-made force measuring equipment collected the output and the grip forces for three seconds. Force measurements along the vertical, coronal and sagittal axes were randomly repeated three times. Results: The pulling was strongest and the pushing was weakest in all directions. The effect of motion on the output forces varied in different directions. The corresponding grip force increased in the order of pushing, pulling, clockwise twisting, and counter clockwise twisting in all directions. The maximal output and their grip forces were highly correlated but the relationship was affected by motion and direction. The regression coefficient was greatest in pulling and smallest in clockwise twisting. Conclusion: The effect of motion on the output forces varied in different directions. The maximal output and their grip forces were correlated but the relationship was affected by motion and direction. Application: Findings of this study can be valuable information for industrial designers to develop more productive hand tools and work stations to help preventing the musculoskeletal disorders at work.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.3
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• pp.10-16
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• 2005

This paper suggested the sulfur lamp power supply using Fuzzy Gain Scheduling(FGS), which was designed and confirmed the performance through manufacturing. it was based on Series Resonant Half Bridge Inverter(SRHBI), so that was applied Pulse Frequency Modulation(PFM), Zero Voltage Switching(ZVS), soft switching and soft start for input power variation and output power compensation. In order to get the lengthened life time of magnetron and stabilized output or power, power ratter and efficiency were improved by fuzzy gain algorism. It also made it possible to get not the existing foxed output power but continuous variable output power$(900\~1250[W])$. The manufactured power supply showed good results in input power $220[V]{\pm}15[\%]$ with stabilized output of power, luminous efficiency 97[1m/W] and power factor $96[\%]$.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.5
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• pp.400-409
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• 2001

A new phase-shifted parallel-input/series-output(PISO) dual converter for tush-power step-up applications has been proposed. Since the proposed converter shows a low switch turn-off voltage stress, switching devices with low conduction loss can be employed in order to improve the power conversion efficiency. Moreover, it features a low output capacitor root-mean-square(RMS) current stress, low input current and output voltage ripple contents, and fast control-to-output dynamics compared to its PWM counterpart. In this paper, the operation of the proposed converter is analyzed in detail and its mathematical models and steady-state solutions are presented. A comparative analysis with the conventional PWM PISO dual converter is also provided. To confirm the operation, features, and validity of the Proposed converter, experimental results from an 800W, 24-350Vdc prototype are presented.

• Journal of Power Electronics
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• v.4 no.3
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• pp.138-151
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• 2004

In this paper, a constant frequency phase shifting PWM-controlled voltage source full bridge-type series load resonant high-frequency inverter using the $4^{th}$ generation IGBT power modules is presented for innovative consumer electromagnetic induction heating applications, such as a hot water producer, steamer and super heated steamer. The bridge arm side link passive capacitive snubbers in parallel with each power semiconductor device and AC load side linked active edge inductive snubber-assisted series load resonant tank soft switching inverter with a constant frequency phase shifted PWM control scheme is evaluated and discussed on the basis of the simulation and experimental results. It is proved from a practical point of view that the series load resonant and edge resonant hybrid high-frequency inverter topology, what is called, DE class type, including the variable-power variable-frequency regulation function can expand zero voltage soft switching commutation area even under low output power setting ranges, which is more suitable and acceptable for newly developed induction heated dual pack fluid heaters. Furthermore, even the lower output power regulation mode of this high-frequency load resonant tank inverter circuit is verified so that this inverter can achieve ZVS with the aid of the single auxiliary inductor snubber.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.3
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• pp.224-230
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• 2016

In this study, a single-power-conversion series-resonant ac-dc converter with high efficiency and high power factor is proposed. The proposed ac-dc converter consists of single-ended primary-inductor converter with an active-clamp circuit and a voltage doubler with series-resonant circuit. The active-clamp circuit clamps the surge voltage and provides zero-voltage switching of the main switch. The series-resonant circuit consists of leakage inductance $L_{lk}$ of the transformer and resonant capacitors $ C_{r1}$ and $ C_{r2}$. This circuit also provides zero-current switching of output diodes $D_1$ and $D_2$. Thus, the switching loss of switches and reverse-recovery loss of output diodes are considerably reduced. The proposed ac-dc converter also achieves high power factor using the proposed control algorithm without the addition of a power factor correction circuit and a dc-link electrolytic capacitor. A detailed theoretical analysis and the experimental results for a 1kW prototype are discussed.