Interleaved ZVS DC/DC Converter with Balanced Input Capacitor Voltages for High-voltage Applications

Abstract

A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to $V_{in}/2$. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.

I. INTRODUCTION

High-voltage converters have been studied and proposed for railway electrical systems [1], ship electric power distribution systems [2], and three-level medium power converters [3]-[5]. Three-level or multilevel converters/inverters [3]-[5] with clamped diodes, capacitors, or series H-bridge circuits have been proposed to reduce the voltage rating of power devices. To achieve compact size, high power density, and high circuit efficiency in modern power products, power switches with high switching frequency and low voltage rating can be adopted in medium-power converters. Thus, three-level converters can use MOSFETs to limit the voltage stress of power switches to Vin/2. Compared with two-level converters, three-level converters have more circuit components and higher cost. However, power switches are operated in hard switching mode if converters have high switching frequency. This condition reduces circuit efficiency. Therefore, three-level converters with soft switching techniques [6]-[13] were developed to reduce the switching losses. Thus, all power switches can be switched on at zero current switching (ZCS) or zero voltage switching (ZVS) within the desired load range. The leakage inductance or external inductance of the transformer and the output capacitance of power switches are resonant at the transition interval. The drain-to-source voltage of MOSFETs can be decreased to zero voltage before MOSFETs are switched on. Therefore, if MOSFETs are switched on under ZVS, circuit efficiency is improved to achieve high switching frequency.

This study presents an interleaved soft switching DC/DC converter for high-voltage and medium-power applications. This converter is characterized by low switching loss, ZVS turn-on, and low voltage rating of MOSFETs. Two circuit modules are adopted, and the interleaved PWM scheme is used to share load current and reduce the ripple currents at input and output capacitors. Thus, the size of the input and output capacitors is reduced. In each circuit module, two input capacitors and two half-bridge converters are connected in series at the high voltage side to limit the voltage rating of MOSFETs to Vin/2. Therefore, power MOSFETs with 500 V voltage rating can be used in DC converters with 800 V input voltage. Two balance capacitors are connected in series between the AC sides of two half-bridge legs to balance two input split capacitor voltages automatically in each switching style. The primary windings of two transformers are connected in series to balance the secondary winding currents. Thus, power can be equally transferred to output load through two center-tapped rectifiers. Asymmetric PWM is adopted to generate the appropriate signals and regulate output voltage. MOSFETs can be switched on at ZVS within the desired load range on the basis of the resonant behavior of the MOSFET output capacitance and the transformer leakage inductance. The operation principle, circuit analysis, and design example of the proposed converter are discussed in detail. To verify the performance of the proposed converter, experiments are conducted with the use of a 1.8 kW prototype .

 

II. CIRCUIT CONFIGURATION

For a general single-phase AC/DC converter, the conventional half-bridge and full-bridge circuit topologies are adopted in the second stage DC/DC converter to regulate output voltage. The voltage stress of the power switches in these circuit topologies is set at DC input bus voltage Vin. Power MOSFETs with 600 V voltage stress are normally adopted for half-bridge and full-bridge converters and are used after single-phase power factor correction (PFC). For three-phase AC/DC converters with PFC function, 900 V voltage stress MOSFETs or 1200 V IGBTs are adopted in the second stage DC/DC converter. The two half-bridge converters shown in Fig. 1 are connected in series at the high voltage side to reduce the voltage rating of power switches to Vin/2. Meanwhile, these converters are connected in parallel at the low-voltage side to reduce the current rating of passive and active components. The main drawback of this circuit topology is that the two input split capacitor voltages can be unbalanced and thus result in unbalanced output inductor currents.

The circuit configuration of the proposed converter is shown in Fig. 2. The DC bus voltage after three-phase PFC is normally within the range of 750 V to 800 V. Two input split capacitor voltages VCdc1 and VCdc2 can be automatically balanced by the clamped capacitors Cc1–Cc4. The proposed DC/DC converter has two circuit modules that share the load current. The interleaved PWM with a 90-degree phase shift is adopted to generate the appropriate switching signals and regulate output voltage. Thus, the ripple currents at the input and output capacitors can be reduced. Each circuit module in the proposed converter has two half-bridge converters in series. For circuit module 1, the first half-bridge converter includes Cdc1, S1, S2, Lr1, T1, T2, Cr1, Cr2, Cc1, D1, D2, Lo1, and Co. The second half-bridge converter includes the components Cdc2, S3, S4, Lr1, T1, T2, Cr3, Cr4, Cc2, D3, D4, Lo2, and Co. Vin and Vo are the input and output DC bus voltages, respectively. Co is the output capacitance, and Ro is the load resistance. Cc1–Cc4 are the DC blocking capacitances. Cr1–Cr8 are the output capacitances of MOSFETs S1–S8, respectively. Lr1 and Lr2 are the resonant inductances, Lm1–Lm4 are the magnetizing inductances and Lo1–Lo4 are the output inductances of transformers T1–T4, respectively. D1–D8 are the rectifier diodes. The asymmetric PWM scheme is used to control MOSFETs S1–S8. S1 and S3 have the same PWM signals, whereas S2 and S4 have the same PWM waveforms. However, S1 and S2 complement each other with dead time to enable the ZVS operation. The gate signals of S5–S8 are phase-shifted by one-fourth of the switching period with respect to the gate signals of S1–S4. Therefore, the inductor currents iLr1 and iLr2 are interleaved. Cdc1 and Cdc2 are input capacitors that split the input voltage (VCdc1=VCdc2=Vin/2). Cc1 and Cc2 are connected in series between AC terminals a and b to balance VCdc1 and VCdc2 automatically. For example, the voltage across Cc1 and Cc2 is equal to VCdc1 if S1 and S3 are conducting while S2 and S4 are in the off-state. Meanwhile, the voltage across Cc1 and Cc2 is equal to VCdc2 if S1 and S3 are in the off-state while S2 and S4 are conducting. Based on the on/off states of S1–S8, two split capacitor voltages VCdc1=VCdc2=Vin/2 and the voltage stress of S1–S8 are equal to Vin/2. In the proposed converter, the primary windings of transformers T1 and T2 are connected in series to balance iLo1 and iLo2 automatically. In the same manner, the output inductor currents iLo3 and iLo4 are also balanced. If power is delivered through two balanced circuit modules, then the current rating of each output inductor is equal to Io/4.

Fig. 1Circuit configuration of two series half-bridge converter for high-input-voltage and high-current applications.

Fig. 2Circuit configuration of the proposed interleaved ZVS converter.

 

III. OPERATION PRINCIPLE

Fig. 3.Key waveforms in a switching cycle (a) circuit module 1 (b) the proposed converter.

The main PWM waveforms of circuit module 1 in the proposed converter are given in Fig. 3(a). The duty cycle of S1 and S3 is δ, and that of S2 and S4 is 1-δ. The circuit modules are controlled by an interleaved PWM scheme. The gate signals of S5–S8 are phase-shifted by Ts/4 with respect to the gate signals of S1–S4, respectively. Fig. 3(b) shows the main waveforms of the proposed interleaved DC/DC converter. The following assumptions about the proposed converter are made to simplify the system analysis:

Circuit modules 1 and 2 exhibit the same behavior. Thus, only circuit module 1 is discussed to simplify the circuit analysis. Based on the on/off states of S1–S4 and D1–D4, eight operating modes exist in circuit module 1 during one switching cycle. Fig. 4 shows the equivalent circuits of eight operation modes in a switching cycle. S1, S3, and D1–D4 are already conducting before time t0.

Mode 1 [t0≤t>Lr, the magnetizing inductor voltages vLm1 and vLm2 are approximately vCc2/2 or (Vin/2-vCc1)/2. The inductor currents iLo1 and iLo2 are increasing in this mode. Power is transferred from input voltage to output load in this time interval. At t1, S1 and S3 are both off.

Mode 2 [t1≤t0, Cr1 and Cr3 are charged linearly, whereas Cr2 and Cr4 are discharged linearly. At t2, vCr2 and vCr3 are equal to vCc1 and vCc2, respectively.

Mode 3 [t2≤t

The dead time td between S1 and S2 must be greater than the time interval Δt13 to achieve ZVS turn-on for S2 and S4.

Mode 4 [t3≤t0, the anti-parallel diodes of S2 and S4 are conducting. Therefore, S2 and S4 can be switched on at this moment to achieve ZVS. Given that D1–D4 are still in the commutation state, the inductor voltage vLr1=-(Vin/2-vCc2)=-vCc1, and iLr1 is decreasing. At t4, iD1 and iD3 are decreasing to zero. The current variation of Lr1 is ΔiLr1 = Io /(2n) . The time interval in this mode is given by

Fig. 4.Operation modes of circuit module 1 in a switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7. (h) Mode 8.

Given that S2, S4, and D1–D4 are conducting, the duty loss in mode 4 is expressed as

Mode 5 [t4≤t

Mode 6 [t5≤t

Mode 7 [t6≤t

The dead time td between S1 and S2 must be greater than the time interval Δt57 to achieve ZVS turn-on for S1 and S3.

Mode 8 [t7≤t

The duty loss in mode 8 is given by

The circuit operations of the proposed converter in a switching cycle are finally completed.

 

IV. CIRCUIT CHARACTERISTICS

Given that Cr1–Cr8 << Cc1–Cc4, the charge and discharge times of Cr1–Cr8 at turn-on and turn-off can be neglected. Only modes 1, 4, 5, and 8 are considered in circuit module 1 to derive the voltage conversion ratio of the proposed converter. From the volt-second balance on (Lr1, Lm1, and Lm2) and (Lr2, Lm3, and Lm4), the average capacitor voltages VCc1–VCc4 are expressed as

where δ is the duty cycle of S1, S3, S5, and S7. We apply the volt-second balance to Lo1–Lo4 in steady state. The voltage conversion ratio of the proposed converter is derived from

where Vf is the voltage drop on diodes D1–D8. Based on (3) and (6)–(8), the output voltage can be rewritten as

The average output inductor currents under steady state are expressed as ILo1=ILo2=ILo3=ILo4=Io/4. The ripple currents on output inductors are given by

Given that iCc1,av=iCc2,av=iCc3,av=iCc4,av=0, the average magnetizing currents ILm1-ILm4 are approximately equal to (1-2δ)Io/(4n). The ripple currents on inductances Lm1–Lm4 can be expressed as

The maximum and minimum magnetizing currents of Lm1–Lm4 are given by

The output inductances of Lo1-Lo4 can be obtained as

The maximum and minimum output inductor currents are expressed as

The average currents on rectifier diodes D1–D8 are expressed as ID1=ID3=ID5=ID7=δIo/4 and ID2=ID4=ID6=ID8=(1-δ)Io/4. The voltage stress of D1, D3, D5, and D7 is δVin/n In the same manner, the voltage stress of rectifier diodes D2, D4, D6, and D8 is (1-δ)Vin/n. The root-mean-square (rms) values of switching currents iS1,rms–iS4,rms are approximately given by

The voltage stresses of S1–S4 are equal to Vin/2. At time t1, the inductor current iLr1 is approximated as

In the same manner, the inductor current iLr1 at t5 is approximated as

If the energy stored in inductor Lr1 at t1 is greater than that in capacitors Cr1–Cr4, then Cr2 and Cr4 can be discharged to zero voltage. The ZVS condition of S2 and S4 is expressed as

If the energy stored in Lr1 at t5 is greater than that in capacitors Cr1–Cr4, then capacitors Cr1 and Cr3 can be discharged to zero voltage. The ZVS condition of S1 and S3 is given by

In the same manner, the ZVS condition of S5 and S7 is given by

The ZVS condition of S6 and S8 is shown in (24).

From (21)–(24), the necessary inductances Lr1 and Lr1 to achieve ZVS turn-on of S1–S8 are derived as

 

V. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS

The proposed converter design is presented in this section. A laboratory prototype with 1.8 kW rated power was built to test the proposed converter. The electrical specifications of the converter are Vin=750 V to 800 V, Vo=24 V, Io=75 A, and fs=100 kHz. The maximum duty cycle of S1 is assumed as 0.45 at Vin=750 V and full load. The maximum duty cycle loss in modes 4 and 8 is assumed to be 15% under a full load with a duty cycle δ=0.5.

Step 1: Resonant inductance

From (26), the resonant inductance of Lr can be derived as

In the prototype circuit, the selected inductances are Lr1 = Lr2 =14μH .

Step 2: Turns ratio of T1–T4

If the voltage drop Vf on diodes D1–D8 is neglected, the turns ratio of T1–T4 is given by

The TDK EER-40C magnetic cores with primary and secondary winding turns of np=45 turns and ns=15 turns, respectively, are adopted for transformers T1–T4. The magnetizing inductance of T1–T4 is 350 μH.

Step 3: Power switches S1-S8

From (17) and (18), the rms currents and voltage stresses of S1–S8 are given by

IRFP460 MOSFETs with VDS=500 V, ID,rms=20 A, RDS,on=0.27 Ω, and Coss=480 pF at 25 V are used for S1–S8.

Step 4: Power diodes D1-D8 and capacitances

The average currents and voltage stresses of D1–D8 are expressed as

The KCU30A30 fast recovery diodes with VRRM=300 V and IF=30 A are used as the rectifier diodes D1–D8. The selected DC blocking capacitances and the output capacitance are Cc1=Cc2=Cc3=Cc4=0.2 μF, Cdc1=Cdc2=470 μF, and Co=4400 μF.

Step 5: Output filter inductances Lo1–Lo4

The ripple current on Lo1-Lo4 is set to 10% of the rated inductor current. From (10), Lo1–Lo4 can be obtained from

where Lo1–Lo4 are set as 16 μH in the prototype circuit.

Step 6: ZVS conditions of S1 and S2

The output capacitance of IRFP460 MOSFETs is 480 pF at 25 V. The equivalent output capacitance Cr at Vin=800 V is given by

From (21) and (22), the minimum inductor current iLr1(t1) and iLr1(t5) to achieve ZVS turn-on for S1–S4 is obtained from

If the ripple currents on the primary and secondary sides in (19) and (20) can be neglected, the minimum load current to achieve ZVS turn-on for (S1 and S3) and (S2 and S4) are approximated in (39) and (40), respectively.

From (39) and (40), S1, S3, S5, and S7 can be switched on under ZVS from 25 A load (approximately 33% load) to 75 A load (100% load). Meanwhile, S2, S4, S6, and S8 can be turned on under ZVS from 19.7 A load (approximately 26% load) to 75 A load (100% load).

Fig. 5.Photograph of the experimental setup.

Fig. 6.Measured PWM waveforms of gate voltages at full load and (a) Vin=750V (b) Vin=800V.

Experiments based on a laboratory prototype, with the circuit parameters derived in the previous section, are presented in this section to verify the effectiveness of the proposed converter. A photograph of the experimental setup is shown in Fig. 5. Fig. 6 shows the measured PWM waveforms of S1–S8 at full load under different input voltages. The PWM signals of S5–S8 were phase-shifted by half of the switching cycle with respect to PWM signals of S1–S4, respectively. Fig. 7 gives the measured gate voltage, drain voltage, and drain current of switches S1 and S2 at Vin=800 V and 26%, 50%, and 100% load conditions. S1 is switched on at hard switching under 26% load and at zero voltage switching under 50% and 100% load condition. However, S2 is switched on under ZVS from 26% load to full load. From the test results in Fig. 7, we can expect that S4, S6, and S8 are also switched on under ZVS from 26% load to full load. Fig. 8 gives the measured voltage waveforms vCdc1, vCdc2, and vCc1+vCc2 at full load. Three capacitor voltages vCdc1, vCdc2 and vCc1+vCc2 are balanced. Fig. 9 shows the measured waveforms of vS1,gs, vS5,gs, iLr1, and iLr2 at full load. When S1 is conducting, iLr1 increases. Meanwhile, iLr1 decreases if S1 switched off. iLr1 and iLr2 are phase-shifted by half of a switching cycle. Fig. 10 gives the measured waveforms of iD1, iD2, iD5, iD6, and iLo1–iLo4 at full load. Fig. 11 shows the output currents iLo1+iLo2 and iLo3+iLo4 of the two circuit modules at full load. The output currents of the two circuit modules balance each other. Fig. 12 shows the measured circuit efficiencies at different load conditions. Based on the load current and the voltage drop on rectifier diodes, the conduction losses on rectifier diodes, MOSFETs, and power semiconductors can be estimated to be approximately 5% to 6%, 1% to 2%, and 6% to 8% of the rated power, respectively. Other power losses are related to the core and copper losses on inductors and transformers, the necessary passive snubber across the rectifier diodes, and some switching losses, such as turn-off losses on MOSFETs and switching losses on rectifier diodes. The rectifier diodes can be replaced by synchronous rectifiers to increase circuit efficiency by approximately 2% to 4%. Low loss MOSFETs and cores can also be adopted to increase circuit efficiency.

Fig. 7.Measured PWM waveforms of gate voltage, drain voltage, and drain current: (a) S1 under 26% load, (b) S2 under 26% load, (c) S1 under 50% load, (d) S2 under 50% load, (e) S1 under 100% load, and (f) S2 under 100% load.

Fig. 8.Measured voltage waveforms vCdc1, vCdc2 and vCc1+vCc2 at full load and 800 V input voltage.

Fig. 9.Measured waveforms of vS1,gs, vS5,gs, iLr1 and iLr2 at full load.

Fig. 10.Measured waveforms of iD1, iD2, iD5, iD6 and iLo1-iLo4 at 100% load.

Fig. 11.Measured waveforms of iLo1+iLo2, iLo3+iLo4 and iLo1+iLo2+iLo3+iLo4 at 100% load.

Fig. 12.Measured circuit efficiencies at different load conditions.

 

VI. CONCLUSIONS

A new parallel DC/DC converter for applications with high input voltage and high load current is presented. The proposed converter is characterized by 1) ZVS turn-on for all switches from 33% load to 100% load, 2) Vin/2 voltage stress of power switches, and 3) low ripple currents at input and output sides when using the interleaved PWM scheme. Two half-bridge converters are connected in series to reduce the voltage stress of power switches at Vin/2. Thus, MOSFETs with 500 V voltage stress are used for 800 V input voltage applications. Two series capacitors connected at the AC terminals of two half-bridge converters are used to balance two input capacitor voltages automatically. A PWM scheme is used to generate PWM signals and regulate output voltage, such that power switches can be switched on under ZVS within the desired load range. System analysis, operation mode, circuit characteristics, and design of the proposed converter are discussed in detail. Finally, experiments with the 1.8 kW prototype are conducted to verify the effectiveness of the proposed converter.