• Journal of Korean Library and Information Science Society
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• v.14
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• pp.39-69
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• 1987

The purpose of this research is to analyze the differences between literature (Belles-letters) class in DDC 19 and literature class in KDC 3. The results of the study can be summarized as follows : 1. The section of philosophy and theory of literature in DDC was subdivided according to the properties as including subsection of theory of criticism but KDC didn't subdivide this section. 2. In DDC, the subsections of 'rhetoric in specific languages' and 'rhetoric of specific kinds of composition' in rhetoric section was established and can subdivide according to each languages and subjects. These considerations can be useful as compared with KDC. 3. In DDC, collections or criticism of several literatures in specific forms can be more subdivide according to specific aspects or features dealing with in the collections or criticism by a n.0, pplying Table 3-A when specified more than the literary form. 4. Reviewing a notational rank to be assigned in literatures of specific languages, Latin literature and Classical Greek literature to be ranked in division in DDC was established as subsection in KDC to treat them as literatures of minor languages. 5. The DDC can sometimes a n.0, pply, in literatures of all languages, the notations of Table 3 to be subdivided again as specific kinds of literary forms, but KDC subdivided literary forms as specific kinds of each forms in only Korean, Chinese, Japanese literature. 6. In DDC, even literatures of minor languages are provided with 'the period table for the specific literature' under each literature of specific languages in schedules and these period tables can be a n.0, pplied a n.0, ppropriately, but period numbers in KDC was established in only Korean, Chinese, Japanese literature. 7. The optional use of letter prefixes or special numbers such as 828.99 to distinguish literatures of countries other than the "mother country" which makes the use of period tables feasible, but the KDC can only use to distinguish without the function of dividing a period such as DDC. 8. According to a n.0, pplying Table 3 and 3-A also in literatures of specific languages(810-890), a literature of specific languages, a specific literary form in literature of specific languages and a literature or literary form of specific period, in case of a n.0, pplying 'form divisions 08-09', can subdivide again by a specific aspect or feature dealing with in the works when specified. 9. For grasping the rate of subdividing, after selecting several sample-titles in literary field, they classified by DDC and KDC and gave a definite score in accordance with analytic small subjects. According to the results, the rate of subdividing in literature class of KDC is proved as less 22.8% than DDC. than DDC.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.9 no.5
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• pp.255-265
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• 2014

Job creation is foundation for wealth creation of the individual personal and important social activities that can solve the problem through increased economic activity and decreased population of unemployment. Jab creation contributes to the best way to solve social problems by acting as mediator of economic stability by establishment to a virtuous cycle between growth and employment and providing the foundation for sustainable growth. In this study, the factors affect on entrepreneurship and professional values were studied on the vocational personality types of student. As a result of this study, Vocational personality types positive commitment to the entrepreneurship. Realistic, exploratory, artistic, social, persuasive and customary factors also positive commitment the entrepreneurship. Vocational personality types positive commitment to the professional values. Professional values positive commitment to the entrepreneurship. However, the professional value factors which are self-actualization, safety, power, independence, community service and leadership depend on entrepreneurship. Therefore, in order to improve the success rate of student start ups, the appropriate selection of optional items of start ups and entrepreneurship education at the right time to establish a business plan by the type of vocational personality types and should provide the opportunity to encounter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• The KIPS Transactions:PartC
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• v.15C no.5
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• pp.399-408
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• 2008

Mobile WiMAX provides wireless broadband services for data communication based on IP protocol. The limitation of physical bandwidth in the radio links may cause performance degradation in providing wireless broadband services in WIMAX. To enhance the efficiency of the radio link utilization, Payload Header Suppression (PHS) is defined as an optional header compression mechanism for mobile WiMAX. It has, however, a very limited compression capability since it has very restrictive compression fields. In this paper, hence, we assumed the application of Robust Header Compression (ROHC), a header compression scheme proposed for links characterized by high bit error ratios, long round-trip times (RTT), and scarce resource, to Mobile WiMAX, and studied its performance. Previous studies on ROHC performance merely focused on the impact of high bit error rate. However, bit error is virtually transparent to ROHC in the wireless systems like WiMAX, since the MAC provides the bit error checking function. In order to evaluate the performance of ROHC in the Mobile WiMAX environments, therefore, we evaluated the performance of ROHC with respect to the packet losses instead of bit error. We investigated the impact of the ROHC parameters that are recommended for the implementation in the ROHC and compared the performance of ROHC with PHS.

• Journal of Korean Neurosurgical Society
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• v.63 no.5
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• pp.590-597
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• 2020

Objective : Covered stenting is an optional strategy for traumatic carotid pseudoaneurysm, especially in malignant conditions of potential rupture, but the long-term outcomes are not clear. Our aim was to determine if covered stenting is an effective option for traumatic carotid pseudoaneurysm with promising long-term outcomes. Methods : Self-expanding Viabahn and balloon-expandable Willis covered stents were separately implanted for extra- and intracranial traumatic carotid pseudoaneurysm. The covered stent was placed across the distal and proximal pseudoaneurysm leakage under roadmap guidance. Procedural success was defined as technical success (complete exclusion of the pseudoaneurysm and patency of the parent artery) without a primary end point (any stroke or death within 30 days after the procedure). Long-term outcomes were evaluated as ischemic stroke in the territory of the qualifying artery by clinical follow-up through outpatient or telephone consultation and as the exclusion of the pseudoaneurysm and patency of the parent artery by imaging follow-up through angiography. Results : Five patients with traumatic carotid pseudoaneurysm who underwent covered stenting were enrolled. The procedural success rate was 100%. No ischemic stroke in the territory of the qualifying artery was recorded in any of the five patients during a mean clinical follow-up of 44±16 months. Complete exclusion of the pseudoaneurysm and patency of the parent artery were maintained in all five patients during a mean imaging follow-up of 39±16 months. Conclusion : Satisfactory procedural and long-term outcomes were obtained, suggesting that covered stenting is an effective option for traumatic carotid pseudoaneurysm.

• Journal of Digital Convergence
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• v.15 no.4
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• pp.91-105
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• 2017

Korea is rapidly becoming a multicultural society in recent years, and the number of multicultural families in 2015 exceeds 3.5% and 800,000. Also, as international marriage rate exceeds 10% by 2016, the number of multicultural families is expected to steadily increase. This study is a design of a metadata application profile as part of the foundation for providing learning resources and content tailored to the needs and preferences of married immigrant women and multicultural family members who need to adapt to Korean society. In order to verify the necessity of the research, we conducted an in-depth interview by screening consumer groups, and analyzed the relevant international and Korean national standards as de-jure standards for the design of metadata standard profiles. Then, we analyzed the contents characteristics for multicultural members, and organized the necessary metadata elements into profiles. We defined the mandatory/optional conditions to reflect the needs of content providers. This study is meaningful in that the study analyzes the educational needs of married immigrant women and presents the necessary metadata standards to develop and service effective educational content, such as korean-to-korean conversion system, personalized learning contents recommendation service, and learning management system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.69-76
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• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• Journal of the Korean Society for information Management
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• v.40 no.3
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• pp.245-271
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• 2023

The purpose of this study was to assess the perception of e-book subscription services among the digitally native generation in their twenties, who have a high e-book usage rate. This study employed a mixed-methods approach, combining survey responses and usability testing. It aimed to assess the awareness and usage of e-book subscription services among university students in their twenties, a demographic known for their high utilization of electronic devices and e-books. The survey was conducted among 202 university students, and the responses were categorized and examined based on whether they were users or non-users. As a result of the survey, I found there is different awareness of e-book between users and non-users, on the other hand, convenience and portability are the strong point of e-books for users and non-users commonly also. Usability testing was performed on a group of 10 university students in their twenties who had not previously used the 'Millies Library' application, which is renowned as the most widely-used e-book platform. Following the experiment, participants expressed positive feedback regarding various optional features, convenience, design, and cost-effectiveness. However, they also had negative reactions concerning touch errors, malfunctions, functional practicality, a lack of interest, system issues, and the absence of a library.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.