• Title/Summary/Keyword: On-chip bus

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Fast and Accurate Performance Estimation of Bus Matrix for Multi-Processor System-on-Chip (MPSoC) (멀티 프로세서 시스템-온-칩(MPSoC)을 위한 버스 매트릭스 구조의 빠르고 정확한 성능 예측 기법)

  • Kim, Sung-Chan;Ha, Soon-Hoi
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.11
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    • pp.527-539
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    • 2008
  • This paper presents a performance estimation technique based on queuing analysis for on-chip bus matrix architectures of Multi-Processor System-on-Chips(MPSoCs). Previous works relying on time-consuming simulation are not able to explore the vast design space to cope with increasing time-to-market pressure. The proposed technique gives accurate estimation results while achieving faster estimation time than cycle -accurate simulation by order of magnitude. We consider the followings for the modeling of practical memory subsystem: (1) the service time with the general distribution instead of the exponential distribution and (2) multiple-outstanding transactions to achieve high performance. The experimental results show that the proposed analysis technique has the accuracy of 94% on average and much shorter runtime ($10^5$ times faster at least) compared to simulation for the various examples: the synthetic traces and real-time application, 4-channel DVR.

A Reconfigurable Image Processing SoC Based on LEON 2 Core (LEON 2 코어 기반 재구성 가능 영상처리 SoC 개발)

  • Lee, Bong-Kyu
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.7
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    • pp.1418-1423
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    • 2009
  • This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

The Design of Hardware MPI Units for MPSoC (MPSoC를 위한 저비용 하드웨어 MPI 유닛 설계)

  • Jeong, Ha-Young;Chung, Won-Young;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.1B
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    • pp.86-92
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    • 2011
  • In this paper, we propose a novel hardware MPI(Message Passing Interface) unit which supports message passing in multiprocessor system which use distributed memory architecture. MPI Hardware unit processes data synchronization, transmission and completion, and it supports processor non-blocking operation so it reduces overhead according to synchronization. Additionally, MPI hardware unit combines ready entry, request entry, reserve entry which save and manage the synchronized messages and performs the multiple outstanding issue and out of order completion. According to BFM(Bus Functional Model) simulation result, the performance is increased by 25% on many to many communication. After we designed MPI unit using HDL, with synopsys design compiler we synthesized, and for synthesis library we used MagnaChip $0.18{\mu}m$. And then we making prototype chip. The proposed message transmission interface hardware shows high performance for its increase in size. Thus, as we consider low-cost design and scalability, MPI hardware unit is useful in increasing overall performance of embedded MPSoC(Multi-Processor System-on-Chip).

Design and Implementation of ARM based Network SoC Processer (ARM 기반의 네트워크용 SoC(System-on-a-chip) 프로세서의 설계 및 구현)

  • 박경철;나종화
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04d
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    • pp.286-288
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    • 2003
  • 본 논문에서는 서로 다른 네트워크간의 다양한 프로토콜과 이종의 트래픽을 동시에 처리할 수 있는 네트워크용 SoC (System-on-a-Chip) 프로세서를 구현하였다. 제작된 네트워크 SoC 프로세서는 ARM 프로세서 코어와 ATM(Asynchronous Transfer Mode) 블록, 10/100 Mbps 이더넷 볼록, 스케쥴러, UART 등을 이용하였고 각 블록은 AM8A (Advanced Microcontroller Bus Architecture) 버스로 연결하였다. SoC 프로세서는 CADENCE사의 VerilogHDL을 이용하여 설계하였고 0.35$\mu\textrm{m}$ 셀 라이브러리를 이용하여 검증하였다. 구현된 칩은 총 게이트수가 312,000개이며 칠의 최대 동작 주파수는 50MHz 이다.

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A Concurrent Testing of DRAMs Utilizing On-Chip Networks (온칩네트워크를 활용한 DRAM 동시 테스트 기법)

  • Lee, Changjin;Nam, Jonghyun;Ahn, Jin-Ho
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.2
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    • pp.82-87
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    • 2020
  • In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

Design of an FPGA-based IP Using SPARTAN-3E Embedded system

  • Moon, Sang-Ook
    • Journal of information and communication convergence engineering
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    • v.9 no.4
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    • pp.428-430
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    • 2011
  • Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embedded systems.

The arbiter for performance improvement of bus architecture (버스 아키텍처 성능 향상을 위한 중재 장치)

  • Lee, Keun-Hwan;Lee, Kook-Pyo;Yoon, Yung-Sup;Kang, Seong-Jun
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.569-570
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    • 2008
  • This paper proposed a new arbitration method in arbiter which is one of bus system components for the design of SoC. Considering compatibility between IP and bus system, the performance of bus system can change the performance of SoC chip. The proposed arbitration method achieved the performance improvement with high efficiency depending on the environment in use.

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Bus Splitting Techniques for Low Power SoC Design (저 전력 시스템 온 칩 설계를 위한 버스 분할 기술)

  • Lim Hoyeong;Yoon Misun;Shin Hyunchul;Park Sungju
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.6
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    • pp.324-332
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    • 2005
  • In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

ASIC Design of OpenRISC-based Multimedia SoC Platform (OpenRISC 기반 멀티미디어 SoC 플랫폼의 ASIC 설계)

  • Kim, Sun-Chul;Ryoo, Kwang-Ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.281-284
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    • 2008
  • This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

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Modeling & Analysis of the System Bus on the SoC Platform (SoC 플랫폼에서 시스템 버스의 모델링 및 해석)

  • Cho Young-shin;Lee Je-hoon;Cho Kyoung-rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.12
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    • pp.35-44
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    • 2005
  • SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.