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A Concurrent Testing of DRAMs Utilizing On-Chip Networks  

Lee, Changjin (Hoseo University, School of Electronics and Display Engineering)
Nam, Jonghyun (Hoseo University, School of Electronics and Display Engineering)
Ahn, Jin-Ho (Hoseo University, School of Electronics and Display Engineering)
Publication Information
Journal of the Semiconductor & Display Technology / v.19, no.2, 2020 , pp. 82-87 More about this Journal
Abstract
In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.
Keywords
On-Chip Networks; Network-On-Chip; Multi-Site Test; Memory Test;
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Times Cited By KSCI : 3  (Citation Analysis)
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