Browse > Article

Modeling & Analysis of the System Bus on the SoC Platform  

Cho Young-shin (Dep. of Computer and Communication Engineering, Chungbuk National University)
Lee Je-hoon (Dept. of Electrical Engineering Systems, University of Southern California)
Cho Kyoung-rok (Dep. of Computer and Communication Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.12, 2005 , pp. 35-44 More about this Journal
Abstract
SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.
Keywords
SoC; platform; system bus; latency model;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 S. Okada, N. Takada, H. Miura and T. Asaeda, 'System-on-a-chip for digital still camera with VGA-size clip shooting,' IEEE Trans. on Consumer Electronics, Vol. 46, no. 3, pp. 622 -627, Aug. 2000   DOI   ScienceOn
2 MaxSim developer suite user's guide Ver 5.0, AXYS Design Automation Inc., Mar. 2004
3 천익재, 김보관, 'SoC를 위한 통신망 설계 동향,' 전자공학회지, 제 30권, 제 5호, 992-1001쪽, 2003년 9월   과학기술학회마을
4 Wen-Tsuen Chen, Jang-Ping Sheu, 'Performance analysis of multiple bus interconnection networks with hierarchical requesting model,' IEEE Trans. on Computers, vol. 40, no. 7, pp. 834-842, Jul. 1991   DOI   ScienceOn
5 Qing Yang, Laxmi N. Bhuyan, 'Analysis of packet-switched multiple-bus multiprocessor system,' IEEE Trans. on Computers, vol. 40, no. 3, pp. 352-357, Mar. 1991   DOI   ScienceOn
6 John L. K., Yu-cheng Liu, 'Performance model for a prioritized multiple-bus multiprocessor system,' IEEE Trans. on Computers, vol. 45, no. 5, pp. 580-588, May. 1996   DOI   ScienceOn
7 K. Keutzer, A.R. Newton, J.M. Rabaey, A. Sangiovanni-Vincentelli, 'System-level design: orthogonalization of concerns and platform-based design,' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, no. 20, pp. 1523-1543, Dec. 2000   DOI   ScienceOn
8 C. A. Jeferino, M. E. Kreutz, L. Carro and A. A. Susin, 'A study on communication issues for systems-on-chip' in Proc. of 15th Symposium on Integrated Circuits and Systems Design, pp. 121-126, Sept. 2002   DOI
9 AMBA specification Rev2.0, ARM co., May 1999
10 W.O. Cesario, D. Lyonnard, G. Nicolescu, Y. Paviot, Sungjoo Yoo, A.A. Jerraya, L. Gauthier, M. Diaz-Nava, 'Multiprocessor SoC platforms: a component-based design approach,' Design & Test of Computers, IEEE, Vol. 19, no. 6, pp. 52-63, Dec. 2002   DOI   ScienceOn
11 Kyeong Keol Ryu, Eung Shin, V.J. Mooney, 'A comparison of five different multiprocessor SoC bus architectures,' in Proc. of Euromicro Symposium on Digital Systems, Design, pp. 202-209, Sept. 2001   DOI
12 Li Li, inglun Gao, uoren Cheng, uoli Zhang, huzhuan He, 'A new platform-based orthogonal SoC design methodology,' in Proc. of 5th International Conference on ASIC, Vol. 1, no. 3, pp. 428-432, Oct. 2003   DOI