• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.63-69
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• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• Journal of the Korean Physical Society
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• v.73 no.11
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• pp.1712-1715
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• 2018

To study the applications for ferroelectric non-volatile memory and ferroelectric memristor, etc., deposition pressure dependent electric the properties of $(Hf,\;Zr)O_2$ thin films by RF sputtering deposition method were investigated. The bottom electrode was TiN thin film to produce stress effect on the formation of orthorhombic phase and top electrode was Pt thin film by DC sputtering deposition. Deposition pressure was varied along with the same other deposition conditions, for example, sputtering power, target to substrate distance, post-annealing temperature, annealing gas, annealing time, etc. The structural and electric properties of the above thin films were investigated. As a result, it is confirmed that the electric properties of the $(Hf,\;Zr)O_2$ thin films depend on the deposition pressure which affects structural properties of the thin films, such as, structural phase, ratio of the constituents, etc.

• The KIPS Transactions:PartA
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• v.18A no.4
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• pp.135-142
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• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.343-344
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• 2012

It has been known since the mid 1960s that Ag can be photodissolved in chalcogenide glasses to form materials with interesting technological properties. In the 40 years since, this effect has been used in diverse applications such as the fabrication of relief images in optical elements, micro photolithographic schemes, and for direct imaging by photoinduced Ag surface deposition. ReRAM, also known as conductive bridging RAM (CBRAM), is a resistive switching memory based on non-volatile formation and dissolution of a conductive filament in a solid electrolyte. Especially, Ag-doped chalcogenide glasses and thin films have become attractive materials for fundamental research of their structure, properties, and preparation. Ag-doped chalcogenide glasses have been used in the formation of solid electrolyte which is the active medium in ReRAM devices. In this paper, we investigated the nature of thin films formed by the photo-dissolution of Ag into Ge-Se glasses for use in ReRAM devices. These devices rely on ion transport in the film so produced to create electrically programmable resistance states. [1-3] We have demonstrated functionalities of Ag doped chalcogenide glasses based on their capabilities as solid electrolytes. Formation of such amorphous systems by the introduction of Ag+ ions photo-induced diffusion in thin chalcogenide films is considered. The influence of Ag+ ions is regarded in terms of diffusion kinetics and Ag saturation is related to the composition of the hosting material. Saturated Ag+ ions have been used in the formation of conductive filaments at the solid electrolyte which is the active medium in ReRAM devices. Following fabrication, the cell displays a metal-insulator-metal structure. We measured the I-V characteristics of a cell, similar results were obtained with different via sizes, due to the filamentary nature of resistance switching in ReRAM cell. As the voltage is swept from 0 V to a positive top electrode voltage, the device switches from a high resistive to a low resistive, or set. The low conducting, or reset, state can be restored by means of a negative voltage sweep where the switch-off of the device usually occurs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.79-85
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• 2009

In this paper, an accurate current reference using temperature and process compensation current mirror (TPC-CM) is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current. However, the temperature coefficient and magnitude of the reference current are influenced by the process variation. To calibrate the process variation, the proposed TPC-CM uses two binary weighted current mirrors which control the temperature coefficient and magnitude of the reference current. After the PTAT and CTAT current is measured, the switch codes of the TPC-CM is fixed in order that the magnitude of reference current is independent to temperature. And, the codes are stored in the non-volatile memory. In the simulation, the effect of the process variation is reduced to 0.52% from 19.7% after the calibration using a TPC-CM in chip-by-chip. A current reference chip is fabricated with a 3.3V 0.35um CMOS process. The measured calibrated reference current has 0.42% variation for $20^{\circ}$C${\sim}$100$^{\circ}$C.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.191.2-191.2
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• 2015

Details of carrier dynamics in self-assembled quantum dots (QDs) with a particular attention to nonradiative processes are not only interesting for fundamental physics, but it is also relevant to performance of optoelectronic devices and the exploitation of nanocrystals in practical applications. In general, the possible processes in such systems can be considered as radiative relaxation, carrier transfer between dots of different dimensions, Auger nonradiactive scattering, thermal escape from the dot, and trapping in surface and/or defects states. Authors of recent studies have proposed a mechanism for the carrier dynamics of time-resolved photoluminescence CdTe (a type II-VI QDs) systems. This mechanism involves the activation of phonons mediated by electron-phonon interactions. Confinement of both electrons and holes is strongly dependent on the thermal escape process, which can include multi-longitudinal optical phonon absorption resulting from carriers trapped in QD surface defects. Furthermore, the discrete quantized energies in the QD density of states (1S, 2S, 1P, etc.) arise mainly from ${\delta}$-functions in the QDs, which are related to different orbitals. Multiple discrete transitions between well separated energy states may play a critical role in carrier dynamics at low temperature when the thermal escape processes is not available. The decay time in QD structures slightly increases with temperature due to the redistribution of the QDs into discrete levels. Among II-VI QDs, wide-gap CdZnTe QD structures characterized by large excitonic binding energies are of great interest because of their potential use in optoelectronic devices that operate in the green spectral range. Furthermore, CdZnTe layers have emerged as excellent candidates for possible fabrication of ferroelectric non-volatile flash memory. In this study, we investigated the optical properties of CdZnTe/ZnTe QDs on Si substrate grown using molecular beam epitaxy. Time-resolved and temperature-dependent PL measurements were carried out in order to investigate the temperature-dependent carrier dynamics and the activation energy of CdZnTe/ZnTe QDs on Si substrate.

• Korean Journal of Materials Research
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• v.23 no.8
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• pp.405-422
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• 2013

Atomic layer deposition(ALD) is a promising deposition method and has been studied and used in many different areas, such as displays, semiconductors, batteries, and solar cells. This method, which is based on a self-limiting growth mechanism, facilitates precise control of film thickness at an atomic level and enables deposition on large and three dimensionally complex surfaces. For instance, ALD technology is very useful for 3D and high aspect ratio structures such as dynamic random access memory(DRAM) and other non-volatile memories(NVMs). In addition, a variety of materials can be deposited using ALD, oxides, nitrides, sulfides, metals, and so on. In conventional ALD, the source and reactant are pulsed into the reaction chamber alternately, one at a time, separated by purging or evacuation periods. Thermal ALD and metal organic ALD are also used, but these have their own advantages and disadvantages. Furthermore, plasma-enhanced ALD has come into the spotlight because it has more freedom in processing conditions; it uses highly reactive radicals and ions and for a wider range of material properties than the conventional thermal ALD, which uses $H_2O$ and $O_3$ as an oxygen reactant. However, the throughput is still a challenge for a current time divided ALD system. Therefore, a new concept of ALD, fast ALD or spatial ALD, which separate half-reactions spatially, has been extensively under development. In this paper, we reviewed these various kinds of ALD equipment, possible materials using ALD, and recent ALD research applications mainly focused on materials required in microelectronics.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.97-103
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• 2020

Linux Cgroups takes a fundamental role for sharing system resources among multiple containers on container-based cloud computing environment. Especially for I/O resource, Linux Cgroups supports a mechanism for sharing I/O bandwidth in proportion to I/O weight. However, the current mechanism of Linux Cgroups using BFQ I/O scheduler seriously degrades the I/O performance with high bandwidth storage device such as NVMe SSDs. In this paper, we proposed a new feedback based I/O bandwidth sharing scheme for Linux Cgroups which allocates I/O credits to containers according to I/O weights and adjusts the amount of credits to performance fluctuation of NVMe SSDs. The proposed scheme is implemented on Linux kernel 5.3 and evaluated. The evaluation results show that it can share the I/O bandwidth among multiple containers proportionally to I/O weights while improving I/O performance more than twice as high as the existing scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.