A Buffer Architecture based on Dynamic Mapping table for Write Performance of Solid State Disk
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Cho, In-Pyo
((주)고영테크놀러지 R&D)
Ko, So-Hyang (연세대학교 컴퓨터과학과) Yang, Hoon-Mo (연세대학교 컴퓨터과학과) Park, Gi-Ho (세종대학교 전자정보공학대학 컴퓨터공학과) Kim, Shin-Dug (연세대학교 공과대학 컴퓨터과학과) |
1 | Cagdas Dirik, Bruce Jacob, "The Performance of PC Solid-State Disks (SSDs) as a Function of Bandwidth, Concurrency, Device Architecture, and System Organization", ISCA'09, 2009. DOI |
2 | A. Ban, "Flash file system", United States Patent, no. 5,404,485, April 1995. |
3 | S.Y. Kim and S.I. Jung, "A Log-based Flash Translation Layer for Large NAND flash memory", Advanced Communication Technology, Vol.3, pp.1641-1644, February, 2006. |
4 | J.D. Kim, J.M. Kim, S.H. Noh, S.L. Min, Y.H. Cho, "A Space-Efficient Flash Translation Layer for Compact Flash Systems", IEEE Transactions on Consumer Electronics, Vol.48, No.2, May, 2002. DOI ScienceOn |
5 | J.H. Yoon, E.H. Nam, H. Kim, B.S. Kim, S.L. Min and Y. Cho, "Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture", IEEE Computer Architecture Letters, Vol.8, No.1, January-June, 2008. DOI ScienceOn |
6 | J.U. Kang, J.S. Kim, C.I. Park, H.J. Park and J.W. Lee, "A Multi-channel Architecture for High-performance NAND flash-based storage system", Journal of systems architecture: the EUROMICRO Journal, Vol.53, Issue 9, September, 2007. DOI ScienceOn |
7 | S.W. Lee, D.J. Park, T.S. Chung, D.H. Lee, S.W. Park, H.J. Song, "A log buffer-based flash translation layer using fully-associative sector translation" , Journal of Embedded Computing Systems(TECS), Vol.6, Issue 3, July, 2007. DOI |
8 | L.P Chang, "Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs", Design Automation Conference, pp.428-433, 2008. |
9 | T.S. Chung, D.J. Park, S. Park, D.H. Lee, S.W. Lee, H.J. Song, "A survey of Flash Translation Layer", Journal of Systems Architecture: the EUROMICRO Journal, Vol.55, pp.332-343, 2009. DOI ScienceOn |
10 | J.U. Kang, H.S. Jo, J.S. Kim, J.W. Lee, "A Superblock-based Flash Translation Layer for NAND Flash Memory", EMSOFT'06, 2006. |
11 | J.S Park, H.K Bahn and K. Koh, "Buffer Cache Management for Combined MLC and SLC Flash Memories Using both Volatile and Nonvolatile RAMs", IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, pp.228-235, 2009. DOI |
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