• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.25-32
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• 2009

Recently, research for Network-on-chip(NoC) is progressing. However, due to the increase of system complexity and demand on high performance, conventional copper-based electrical interconnect would be faced with the design limitation of performance, power, and bandwidth. As an alternative to these problems, combined use of Electrical Interconnects(EIs) and Optical Interconnects(OIs) has been introduced. In this paper we propose efficient routing optimization strategy and hybrid switch architecture, which use OIs for critical path and EIs for non-critical path. The proposed method shows up to 25% performance improvement and 38% power reduction.

• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.430-437
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• 2005

In this paper, we proposed a biologically inspired light-adaptive edge detection circuit based on the human retina. A saturating resistive network was suggested for light adaptation and simulated by using HSPICE. The light adaptation mechanism of the edge detection circuit was quantitatively analyzed by using a simple model of the saturating resistive element. A light-adaptive capability of the edge detection circuit was confirmed by using the one-dimensional array of the 128 pixels with various levels of input light intensity. Experimental data of the saturating resistive element was compared with the simulated results. The entire capability of the edge detection circuit, implemented with the saturating resistive network, was investigated through the two-dimensional array of the $64{\times}64$ pixels

• Journal of Sensor Science and Technology
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• v.28 no.5
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.9-17
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• 2015

After its inception in 1994, the Journal of the Microelectronics and Packaging Society has continued to make significant strides in the number and quality of publications within its field. The interest in the microelectronics and packaging research has become more critical as consumer electronic products continue its increasing trend towards thinner and lighter devices that tests the boundaries of electronic devices. This study utilizes social network analysis of all published literature in the Journal for the past 22 years. Using the keywords and abstracts available within each individual article, the publications within the Journal has focused on major topics covering (1) flip chip, (2) reliability, (3) Cu, (4) IMC (intermetallic compounds), and (5) thin film. Using the social network relationship between keywords within articles, flip chip was closely associated with reliability, BGA (ball grid array), contact resistance, electromigration in many of the published research works within the Journal. From the centrality analysis, it was found that flip chip, reliability, Cu, thin film, IMC, and RF (radio frequency) to have a high degree of centrality suggesting these key areas of research have relatively high connectivity with other research topics within the Journal and is central to many of the research fields within the micro-electronics and packaging area. The cohesiveness analysis showed research clustering of five major cohesive sub-groups and was mapped to better understand the major area of research within this field. Research within the field of micro-electronics and packaging converges many disciplines of science and engineering. The continued evolution within this field requires an understanding of the rapidly changing industry environment and the consumer needs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2061-2068
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• 2016

A Bloom filter is a space-efficient data structure popularly applied in many network algorithms. This paper proposes a vectored Bloom filter to provide a high-speed Internet protocol (IP) address lookup. While each hash index for a Bloom filter indicates one bit, which is used to identify the membership of the input, each index of the proposed vectored Bloom filter indicates a vector which is used to represent the membership and the output port for the input. Hence the proposed Bloom filter can complete the IP address lookup without accessing an off-chip hash table for most cases. Simulation results show that with a reasonable sized Bloom filter that can be stored using an on-chip memory, an IP address lookup can be performed with less than 0.0003 off-chip accesses on average in our proposed architecture.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.554-561
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• 2006

In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.595-598
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• 2003

A new classifier is constructed by using a generalized regression neural network (GRNN) in conjunction with a random generator (RC). The RG played a role of generating a number of sets of random spreads given a range for gaussian functions in the pattern layer, The range experimentally varied from 0.4 to 1.4. The DNA sequences consisted 4 types of promoters. The performance of classifier is examined in terms of total classification sensitivity (TCS), and individual classification sensitivity (ICS). for comparisons, another GRNN classifier was constructed and optimized in conventional way. Compared GRNN, the RG-GRNN demonstrated much improved TCS along with better ICS on average.