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XSNP: An Extended SaC Network Protocol for High Performance SoC Bus Architecture  

Lee Chan-Ho (숭실대학교 정보통신전자공학부)
Lee Sang-Hun (숭실대학교 전자공학과)
Kim Eung-Sup (서울대학교 전기 컴퓨터공학부)
Lee Hyuk-Jae (서울대학교 전기 컴퓨터공학부)
Abstract
In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.
Keywords
SNA; SNP; on-chip-bus; SoC bus; on-chip-network; crossbar router; AMBA;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 ARM, Technical Support FAQs [Online], Available: http://www.arm.com/support/faqip/577.html
2 Sanghun Lee, Chanho Lee, Hyuk -jae Lee, 'A New Multi-Channel On-Chip-Bus Architecture for System-On-Chips,' IEEE-SoC Conference, Santa Clara, CA., pp. 305-308, September 2004   DOI
3 이재성, 이혁재, 이찬호, 'SNP: 시스템 온 칩을 위한 새로운 통신 프로토콜' 정보과학회논문지, 시스템 및 이론 제32권 제9호, pp. 465-474, 2005.10   과학기술학회마을
4 IBM, 'CoreConnect Bus Architecture,' 1999
5 F. Moraes, et al. 'Hermes: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip,' Integration the VLSI Journal, 38(1), Oct. 2004, pp. 69-93   DOI   ScienceOn
6 P. Gurrier, A. Greiner, 'A Generic Architecture for On-Chip Packet-Switched Interconnections,' Proceedings of the conference on Design, Automation and Test in Europe, Paris, France, pp. 250-256, 2000   DOI
7 ARM, 'AMBA Specification, Revision 2.0,' 1999
8 W. Peterson, 'WISHBONE SoC Architecture Specification, Revision B.2,' Silicore Corporation, 2001.
9 Inside the New Computer Industry, issue 138, Jan 2001