Browse > Article
http://dx.doi.org/10.6109/jkiice.2022.26.3.355

Microcode based Controller for Compact CNN Accelerators Aimed at Mobile Devices  

Na, Yong-Seok (Department of Electronics Engineering, Chungbuk National University)
Son, Hyun-Wook (Department of Electronics Engineering, Chungbuk National University)
Kim, Hyung-Won (Department of Electronics Engineering, Chungbuk National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.26, no.3, 2022 , pp. 355-366 More about this Journal
Abstract
This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).
Keywords
Microcode; Convolution Neural Network Accelerator; SoC; FPGA;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
연도 인용수 순위
1 K. KRISHNAIAH and Y. RAVINDER, "Design of Memory controller with AXI Bus interface," International Journal of Engineering Science and Generic Research (IJESAR), vol. 2, no. 5, Oct. 2016.
2 J. Redmon, S. Divvala, R. Girshick, and A. Farhadi, "You only look once: Unified, real-time object detection," in Proceedings of IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp. 779-788, 2016.
3 F. Ge, N. Wu, H. Xiao, Y. Zhang, and F. Zhou, "Compact Convolutional Neural Network Accelerator for IoT Endpoint SoC," Electronics, vol. 8, iss. 5, 2019.
4 N. P. Jouppi, C. Young, N. Patil, D. Patterson, G. Agrawal, R. Bajwa, S. Bates, S. Bhatia, N. Boden, A. Borchers, R. Boyle, P. Cantin, C. Chao, C. Clark, J. Coriell, M. Daley, M. Dau, J. Dean, B. Gelb, T. V. Ghaemmaghami, R. Gottipati, W. Gulland, R. Hagmann, C. Richard Ho, D. Hogberg, J. Hu, R. Hundt, D. Hurt, J. Ibarz, A. Jaffey, A. Jaworski, A. Kaplan, H. Khaitan, D. Killebrew, A. Koch, N. Kumar, S. Lacy, J. Laudon, J. Law, D. Le, C. Leary, Z. Liu, K. Lucke, A. Lundin, G. MacKean, A. Maggiore, M. Mahony, K. Miller, R. Nagarajan, R. Narayanaswami, R. Ni, K. Nix, T. Norrie, M. Omernick, N. Penukonda, A. Phelps, J. Ross, M. Ross, A. Salek, E. Samadiani, C. Severn, G. Sizikov, M. Snelham, J. Souter, D. Steinberg, A. Swing, M. Tan, G. Thorson, B. Tian, H. Toma, E. Tuttle, V. Vasudevan, R. Walter, W. Wang, E. Wilcox, and D. H. Yoon, "Indatacenter performance analysis of a tensor processing unit," in 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture, pp. 1-12, Jun. 2017.
5 H. Son, Y. Na, T. Kim, A. A. Al-Hamid, and H. Kim, "CNN Accelerator with Minimal On-Chip Memory Based on Hierarchical Array," in 2021 18th International SoC Design Conference (ISOCC), pp. 411-412, Oct. 2021.
6 Y. H. Chen, T. Krishna, J. S. Emer, and V. Sze, "Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks," IEEE J. Solid-State Circuits, vol. 52, iss. 1, pp. 127-138, Jan. 2017.   DOI
7 X. Zhou, L. Zhang, C. Guo, X. Yin, and C. Zhuo, "A Convolutional Neural Network Accelerator Architecture with Fine-Granular Mixed Precision Configurability," in 2020 IEEE International Symposium on Circuits and Systems, pp. 1-5, 2020.
8 S. Kim, J. Lee, S. Kang, J. Lee, and H. Yoo(2020), "A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, vol. 67, iss. 4, pp. 1181-1193, Apr. 2020.   DOI
9 L. Zhang, X. Zhou, and C. Guo, "A CNN ACCELERATOR WITH EMBEDDED RISC-V CONTROLLERS," in 2021 China Semiconductor Technology International Conference (CSTIC), pp. 1-3, Mar. 2021.
10 Q. Zhao, Y. Nakahara, M. Amagasaki, M. Iida, and T. Yoshida, "A Microcode-based Control Unit for Deep Learning Processors," in 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 139-142, May. 2020.
11 N. Tidala, "High Performance Network On Chip using AXI4 protocol interface on an FPGA," in Proceedings of the 2nd International conference on Electronics, Communication and Aerospace Technology (ICECA 2018), pp. 1647-1651, Mar. 2018.
12 AMBA 4 AXI4 Stream Protocol, Version 1.0.
13 SiFive, Inc.: SiFive U54 Manual, v21.G2.01.00 (2021).
14 K. VeenaH and A. Ali, "Design and Implementation of High Speed DDR SDRAM Controller on FPGA," International Journal of Engineering Research & Technology (IJERT), vol. 4, iss. 7, Jul. 2015.
15 W. Lin, D. Tsai, L. Tang, C. Hsieh, C. Chou, P. Chang, and L. Hsu, "ONNC: A Compilation Framework Connecting ONNX to Proprietary Deep Learning Accelerators," in 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 214-218, Mar. 2019.