• Title/Summary/Keyword: Nano silicon

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Improvement of carrier transport in silicon MOSFETs by using h-BN decorated dielectric

  • Liu, Xiaochi;Hwang, Euyheon;Yoo, Won Jong
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2013.05a
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    • pp.97-97
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    • 2013
  • We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.

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Study on the Silicon Nano-needle Structure for Nano floating Gate Memory Application (나노 부유 게이트 메모리 소자 응용을 위한 실리콘 나노-바늘 구조에 관한 연구)

  • Jung, Sung-Wook;Yoo, Jin-Su;Kim, Young-Kuk;Kim, Kyung-Hae;Yi, Jun-Sin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.12
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    • pp.1069-1074
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    • 2005
  • In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

Fabrication of silicon nano-wire MOSFET photodetector for high-sensitivity image sensor (고감도 이미지 센서용 실리콘 나노와이어 MOSFET 광 검출기의 제작)

  • Shin, Young-Shik;Seo, Sang-Ho;Do, Mi-Young;Shin, Jang-Kyoo;Park, Jae-Hyoun;Kim, Hoon
    • Journal of Sensor Science and Technology
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    • v.15 no.1
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    • pp.1-6
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    • 2006
  • We fabricated Si nano-wire MOSFET by using the conventional photolithography with a $1.5{\mu}m$ resolution. Si nano-wire was fabricated by using reactive ion etching (RIE), anisotropic wet etching and thermal oxidation on a silicon-on-insulator (SOI) substrate, and its width is 30 nm. Logarithmic circuit consisting of a NMOSFET and Si nano-wire MOSFET has been constructed for application to high-sensitivity image sensor. Its sensitivity was 1.12 mV/lux. The output voltage swing was 1.386 V.

Strong Red Photoluminescence from Nano-porous Silicon Formed on Fe-Contaminated Silicon Substrate

  • Kim, Dong-Lyeul;Lee, Dong-Yul;Bae, In-Ho
    • Transactions on Electrical and Electronic Materials
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    • v.5 no.5
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    • pp.194-198
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    • 2004
  • The influences of the deep-level concentration of p-type Si substrates on the optical properties of nano-porous silicon (PS) are investigated by deep level transient spectroscopy (DLTS) and photoluminescence (PL). Utilizing a Si substrate with Fe contaminations significantly enhanced the PL intensity of PS. All the PS samples formed on Fe-contaminated silicon substrates had stronger PL yield than that of reference PS without any intentional Fe contamination but the emission peak is not significantly changed. For the PS 1000 sample with Fe contamination of 1,000 ppb, the maximum PL intensity showed about ten times stronger PL than that of the reference PS sample. From PL and DLTS results, the PL efficiency strongly depends on the Fe-related trap concentration in Si substrates.

Characteristics of Trap in the Thin Silicon Oxides with Nano Structure

  • Kang, C.S.
    • Transactions on Electrical and Electronic Materials
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    • v.4 no.6
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    • pp.32-37
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    • 2003
  • In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

A Study on the Nano-Deformation Behaviors of Single Crystal Silicon and Amorphous Borosilicate Considering the Mechanochemical Reaction (기계화학적 반응을 고려한 단결정 실리콘과 비정질 보로실리케이트의 나노 변형 거동에 관한 연구)

  • 윤성원;신용래;강충길
    • Transactions of Materials Processing
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    • v.12 no.7
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    • pp.623-630
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    • 2003
  • Nanomachining process, static nanoplowing, is one of the most promising lithographic technologies in terms of the low cost of operation and variety of workable materials. In nanomachining process, chemical effects are more dominant factor compared with those by physical deformation or fracture. For example, during the nanoscratch on a silicon surface in the atmosphere, micro protuberances are formed due to the mechanochemical reaction between diamond tip and the surfaces. On the contrary, in case of chemically stable materials, such as ceramic or glass, surface protuberances are not formed. The purpose of this study is to understand effects of the mechanochemical reaction between tip and surfaces on deformation behaviors of hard-brittle materials. Nanometerscale elasoplastic deformation behavior of single crystal silicon (100) was characterized with micro protuberance phenomena, and compared with that of borosilicate (Pyrex glass 7740). In addition, effects of the silicon protuberances on nanoscratch test results were discussed.

A Novel Fabrication Method of the High-Aspect-Ratio Nano Structure (HAR-Nano Structure) Using a Nano X-Ray Shadow Mask (나노 X-선 쉐도우 마스크를 이용한 고폭비의 나노 구조물 제작)

  • Kim Jong-Hyun;Lee Seung-S.;Kim Yong-Chul
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.30 no.10 s.253
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    • pp.1314-1319
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    • 2006
  • This paper describes the novel fabrication method of the high-aspect-ratio nano structure which is impossible by conventional method using a shadow mask and a Deep X-ray Lithography (DXRL). The shadow mask with $1{\mu}m-sized$ apertures is fabricated on the silicon membrane using a conventional UV-lithography. The size of aperture is reduced to 200nm by accumulated low stress silicon nitride using a LPCVD (low pressure chemical vapor deposition) process. The X-ray mask is fabricated by depositing absorber layer (Au, $3{\mu}m$) on the back side of nano shadow mask. The thickness of an absorber layer must deposit dozens micrometers to obtain contrast more than 100 for a conventional DXRL process. The thickness of $3{\mu}m-absorber$ layer can get sufficient contrast using a central beam stop method, blocking high energy X-rays. The nano circle and nano line, 200nm in diameter in width, respectively, were demonstrated 700nm in height with a negative photoresist of SU-8.

Electrochemical Characteristics of Porous Silicon/Carbon Composite Anode Using Spherical Nano Silica (구형 나노 실리카를 사용한 다공성 실리콘/탄소 음극소재의 전기화학적 특성)

  • Lee, Ho Yong;Lee, Jong Dae
    • Korean Chemical Engineering Research
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    • v.54 no.4
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    • pp.459-464
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    • 2016
  • In this study, the electrochemical characteristics of porous silicon/carbon composite anode were investigated to improve the cycle stability and rate performance in lithium ion batteries. In this study, the effect of TEOS and $NH_3$ concentration, mixing speed and temperature on particle size of nano silica was investigated using $St{\ddot{o}}ber$ method. Nano porous Si/C composites were prepared by the fabrication processes including the synthesis of nano $SiO_2$, magnesiothermic reduction of nano $SiO_2$ to obtain nano porous Si by HCl etching, and carbonization of phenolic resin. Also the electrochemical performances of nano porous Si/C composites as the anode were performed by constant current charge/discharge test, cyclic voltammetry and impedance tests in the electrolyte of $LiPF_6$ dissolved inorganic solvents (EC:DMC:EMC=1:1:1vol%). It is found that the coin cell using nano porous Si/C composite has the capacity of 2,006 mAh/g and the capacity retention ratio was 55.4% after 40 cycle.

Optimization of Thermal Performance in Nano-Pore Silicon-Based LED Module for High Power Applications

  • Chuluunbaatar, Zorigt;Kim, Nam-Young
    • International Journal of Internet, Broadcasting and Communication
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    • v.7 no.2
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    • pp.161-167
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    • 2015
  • The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.

One Step Preparation of Spherical Silicon Resins from Immiscible Reaction Mixtures

  • Lee, Da-Yun;Kim, Young-A;Kim, Young-Baek;Kim, Jun-Kyu;Han, Yang-Kyoo
    • Macromolecular Research
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    • v.16 no.4
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    • pp.353-359
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    • 2008
  • Spheres of silicon resins with different compositions were prepared in one-step reaction from mixtures of water and water-insoluble precursors of polysiloxanes (PSO) and polysilsesquioxanes (PSQ) using different amines as catalysts. The presence of PSO and PSQ in the spheres was confirmed by their mechanical properties and FTIR spectroscopy. Spheres of pure PSO were obtained from only dimethoxymethylvinylsiloxane (DMMVS) and 3-mercaptopropylmethyldimethoxysilan (MPMDMS) when the reaction was induced with appropriate catalysts. DMMVS and MPMDMS always gave the most promising results regarding the formation of discrete solid spheres with the minimum tendency to form monolithic solids or fluid-like, premature products. The spheres were characterized by optical microscopy, scanning electron microscopy (SEM), and Fourier transform infrared (FTIR) spectroscopy. The mixtures containing larger amounts of PSO precursors commonly gave lower yields and softer spheres.