• Korean Journal of Materials Research
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• v.18 no.3
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• pp.117-122
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• 2008

Micro-sized bumps on a multi-layered build-up PCB were fabricated by pulse-reverse copper electroplating. The values of the current density and brightener content for the electroplating were optimized for suitable performance with maximum efficiency. The micro-bumps thus electroplated were characterized using a range of analytical tools that included an optical microscope, a scanning electron microscope, an atomic force microscope and a hydraulic bulge tester. The optical microscope and scanning electron microscope analyses results showed that the uniformity of the electroplating was viable in the current density range of $2-4\;A/dm^2$; however, the uniformity was slightly degraded as the current density increased. To study the effect of the brightener concentration, the concentration was varied from zero to 1.2 ml/L. The optimum concentration for micro-bump electroplating was found to be 0.6 ml/L based on an examination of the electroplating properties, including the roughness, yield strength and grain size.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.59-66
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• 2018

In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.8-13
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• 2006

Recent RF SAW filters are made using a HTCC package with a CSP(chip scale Package) technology. This paper describes a development of a new $1.4{\times}1.1\;and\;2.0{\times}1.4mm$ RF SAW liters made by PCB substrate instead of HTCC package, and this technology can reduce the cost of materials down to 40%. We have investigated the multi-layered PCB substrate structures and raw materials to find out the optimal flip-bonding condition between the $LiTaO_3$ wafer and PCB substrates. Also the optimal materials and processing conditions of epoxy laminating film were found out through the experiments which can reduce the bending moment caused by the difference of the thermal expansion between the PCB substrate and laminating film. The new PCB SAW filter shows good electrical and reliability performances with respect to the present SAW filters.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.16-22
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• 2013

A general characterization procedure based on the extraction of a 2n-port admittance matrix corresponding to n uniform coupled lines on the multi-layered substrate using the Finite-Difference Time-Domain (FDTD) technique is presented. In this paper, the frequency-dependent normal mode parameters are obtained from the 2n-port admittance matrix to analyze multi-layered asymmetric coupled line structure, which in turn provides the frequency-dependent propagation constant, effective dielectric constant, and line-mode characteristic impedances. To illustrate the technique, several practical coupled line structures on multi-layered substrate have been simulated. Especially, embedded conductor structures have been simulated. Comparisons with Spectral Domain Method are given, and their results agree well. It is shown that the FDTD based time domain characterization procedure is an excellent broadband simulation tool for the design of multiconductor coupled lines on multilayered PCBs as well as thick or thin hybrid structures.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.55-67
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• 2010

The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.5
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• pp.383-390
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• 2020

Wedge locks have been widely used for spaceborne electronics for mounting or removal of a printed circuit board (PCB) during integration, test and maintenance process. However, it can basically provide a mechanical constraint on the edge of the board. Thus, securing a fatigue life of solder joint for electronic package by limiting board deflection becomes difficult as the board size increases. Previously, additional stiffeners have been applied to reduce the board deflection, but the mass and volume increases of electronics are unavoidable. To overcome the aforementioned limitation, we proposed an application of multi-layered PCB sheet with viscoelastic adhesive tapes to implement high-damping capability on the board. Thus, it is more advantageous in securing the fatigue life of package under launch environment compared with the previous approach. The basic characteristics of the PCB with the multi-layered sheet was investigated through free-vibration tests at various temperatures. The effectiveness of the proposed design was validated through launch vibration test at qualification level and fatigue life prediction of electronic package based on the test results.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.275-280
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• 2001

Recently, the trends of industrial products grow more miniaturization, variety and mass production. Micro drilling which take high precision in cutting work is requested more micro hole and high speed working. Especially, Micro deep hole drilling is becoming more important in a wide spectrum of precision production industries, ranging from the production of automotive fuel injection nozzle, watch and camera parts, medical needles, and thick multi-layered Printed Circuit Boards(PCB) that are demanded for very high density electric circuitry. This paper shows the tool monitoring results of micro drill with tool dynamometer. And additionally, microscope with built-in monitor inspection show the relationship between burr in workpiece and chip form of micro drill machining.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.6
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• pp.300-305
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• 2004

In this paper, new design equations based on the pole-zero analysis for multi-layered interdigital stripline linear group delay bandpass filter with tap input ports are presented. As a design example, a four-pole group delay filter with center frequency of 2.14GHz, bandwidth of 160MHz, and group delay variation of $\pm$0.1nS for LTCC technology or multilayered PCB technology is designed. In the design process, it is not necessary to simulate the entire structure, as the simulation of half structures is sufficient. Good results can be attained after the optimizing process was performed three times using the proposed equations and a commercial EM simulator.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.