• Journal of the Korean Operations Research and Management Science Society
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• v.14 no.2
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• pp.47-47
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• 1989

This paper considers the parallel machines scheduling problem characterized as a multi-objective combinatorial problem. As this problem belongs to the NP-complete problem, genetic algorithms are applied instead of the traditional analytical approach. The purpose of this study is to show how the problem can be effectively solved by using genetic algorithms with a permutation approach. First, a permutation representation which can effectively represent the chromosome is introduced for this problem . Next, a schedule builder which employs the combination of scheduling theories and a simple heuristic approach is suggested. Finally, through the computer experiments of genetic algorithm to test problems, we show that the niche formation method does not contribute to getting better solutions and that the PMX crossover operator is the best among the selected four recombination operators at least for our problem in terms of both the performance of the solution and the operational convenience.

• Journal of the Korean Operations Research and Management Science Society
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• v.32 no.1
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• pp.77-91
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• 2007

In this paper, we present a symbiotic evolutionary algorithm for multi-objective optimization. The goal in multi-objective evolutionary algorithms (MOEAs) is to find a set of well-distributed solutions close to the true Pareto optimal solutions. Most of the existing MOEAs operate one population that consists of individuals representing the entire solution to the problem. The proposed algorithm has a two-leveled structure. The structure is intended to improve the capability of searching diverse and food solutions. At the lower level there exist several populations, each of which represents a partial solution to the entire problem, and at the upper level there is one population whose individuals represent the entire solutions to the problem. The parallel search with partial solutions at the lower level and the Integrated search with entire solutions at the upper level are carried out simultaneously. The performance of the proposed algorithm is compared with those of the existing algorithms in terms of convergence and diversity. The optimization problems with continuous variables and discrete variables are used as test-bed problems. The experimental results confirm the effectiveness of the proposed algorithm.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.12
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• pp.439-446
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• 2016

In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction-based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.

• Journal of the Korea Safety Management & Science
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• v.6 no.4
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• pp.155-170
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• 2004

Among the semiconductor If-chips, unlike memory chips, a majority of Application Specific IC(ASIC) products are produced by customer orders, and meeting the customer specified due date is a critical issue for the case. However, to the one who understands the nature of semiconductor manufacturing, it does not take much effort to realize the difficulty of meeting the given specific production due dates. Due to its multi-layered feature of products, to be completed, a semiconductor product(called device) enters into the fabrication manufacturing process(FAB) repeatedly as many times as the number of the product specified layers, and fabrication processes of individual layers are composed with similar but not identical unit processes. The unit process called photo-lithography is the only process where every layer must pass through. This re-entrant feature of FAB makes predicting and planning of due date of an ordered batch of devices difficult. Parallel machines problem in the photo process, which is bottleneck process, is solved with restricted roll out algorithm. Roll out algorithm is a method of solving the problem by embedding it within a dynamic programming framework. Restricted roll out algorithm Is roll out algorithm that restricted alternative states to decrease the solving time and improve the result. Results of simulation test in condition as same as real FAB facilities show the effectiveness of the developed algorithm.

• Transactions on Electrical and Electronic Materials
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• v.5 no.1
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• pp.19-23
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• 2004

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.529-536
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• 2015

As personal information protection act was recently enforced, a mechanism which saves encrypted personal information has been used to Information Security systems. To use the mechanism, a millions of personal information which are already saved on the system first have to be encrypted. At the moment, it may cause a resource scarcity on server, and also take a lot of time. Thus, this paper suggests a way to encrypt millions of personal information by using multi-server with low specifications and measures its performance on test environment. And, I was compared with the performance of high- specification server. As a compared result, the mechanism with three devices by parallel and distributed processing improved its performance by 128%, and the mechanism with five devices by the same processing improved its performance by 158%.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1778-1790
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• 2018

Based on the requirements and characteristics of multi-zone autonomous decision-making in modern power system, fully distributed computing methods are needed to optimize the economic dispatch (ED) problem coordination of multi-regional power system on the basis of constructing decomposition and interaction mechanism. In this paper, four fully distributed methods based on alternating direction method of multipliers (ADMM) are used for solving the ED problem in distributed manner. By duplicating variables, the 2-block classical ADMM can be directly used to solve ED problem fully distributed. The second method is employing ADMM to solve the dual problem of ED in fully distributed manner. N-block methods based on ADMM including Alternating Direction Method with Gaussian back substitution (ADM_G) and Exchange ADMM (E_ADMM) are employed also. These two methods all can solve ED problem in distributed manner. However, the former one cannot be carried out in parallel. In this paper, four fully distributed methods solve the ED problem in distributed collaborative manner. And we also discussed the difference of four algorithms from the aspects of algorithm convergence, calculation speed and parameter change. Some simulation results are reported to test the performance of these distributed algorithms in serial and parallel.

• Journal of Power Electronics
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• v.18 no.3
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• pp.879-891
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• 2018

A bidirectional dc-dc converter is used in battery energy storage systems owing to the growing requirements of a charging and discharging mode of battery. The magnetic coupling of output or input inductors in parallel-connected multi modules of a bidirectional dc-dc converter is often utilized to reduce the peak-to-peak ripple size of the inductor current. This study proposes a novel design guideline to achieve minimal ripple size of the inductor current under bidirectional power flow. The newly proposed design guideline of optimized coupling factor is applicable to the buck and boost operation modes of a bidirectional dc-dc converter. Therefore, the coupling factor value of the coupled inductor does not have to be optimized separately for buck and boost operation modes. This new observation is explained using the theoretical model of coupled inductor and confirmed through simulation and experimental test.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.6
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• pp.86-92
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• 1993

In this paper, we present a VLSI chip design of Multi-layer Bidirectionsl Associative Memory with good error-correction performance. The MBAM neural chip utilizes inner product implementation schems with binary storage and analog calculation.. Multi-layer can be constructed by direct cascading of these chips, and the number of neurons is expandable by parallel connection of these chips. We made proto-type chips and interface board to test the expansion. Currently the Chip has 32 input nodes, 32 output nodes, and can store up to 48 patterns, 32x48x2 SRAMs are included in the chip.

• Proceedings of the Korean Society of Computer Information Conference
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• 2019.07a
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• pp.97-98
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• 2019

본 논문에서는 대용량의 방송 콘텐츠를 전송하기 위해 다수개의 채널을 결합하여 안정적이고 고속으로 전송하기 위한 방송콘텐츠를 전송하기 위한 테스트베드를 제안한다. 제안하는 테스트베드의 첫 번째 목적은 하나의 방송채널 용량을 초과하는 대용량 방송 콘텐츠를 다수개의 채널을 결합하여 전송하기 위한 것이며, 두 번째 목적은 다채널로 입력된 데이터를 다양한 방법의 병렬 알고리즘을 적용하여 FPGA에 적용한 후 그 결과를 테스트하기 위한 것이다. 이를 위하여 제안하는 테스트베드는 다채널을 위한 입력 보드와 전반적인 제어를 위한 CPU 보드, 병렬 알고리즘 등을 테스트하기 위한 FPGA 보드, 그리고 3개의 보드들을 연결하기 위한 베이스 보드로 구성되었다. 제안하는 테스트베드 환경에서 다채널 대용량의 데이터를 병렬처리 할 수 있는 병렬 알고리즘들을 지속적으로 개발하고 테스트하여 다채널 대용량의 실시간 처리가 가능한 영상처리 시스템을 개발하는 것이다.