DOI QR코드

DOI QR Code

Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy

예측정확도 향상 전략을 통한 예측기반 병렬 게이트수준 타이밍 시뮬레이션의 성능 개선

  • 양세양 (부산대학교 정보컴퓨터공학부)
  • Received : 2016.06.08
  • Accepted : 2016.09.22
  • Published : 2016.12.31

Abstract

In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction-based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.

본 논문에서는 예측기반 병렬 이벤트구동 게이트수준 타이밍 시뮬레이션의 성능 개선을 위한 효율적인 예측정확도 향상 전략을 제안한다. 제안된 기법은 병렬 이벤트구동 로컬시뮬레이션들의 입력값과 출력값에 대한 예측을 이중으로 예측할 뿐만 아니라, 특별한 상황에서는 동적으로 예측할 수 있게 한다. 이중 예측은 첫번째 예측이 틀린 경우에 두번째 정적 예측 데이터로써 새로운 예측을 시도하게 되며, 동적 예측은 실제의 병렬 시뮬레이션 실행 과정 도중에 동적으로 축적되어진 지금까지의 시뮬레이션 결과를 예측 데이터로 활용하는 것이다. 제안된 두가지의 예측정확도 향상 기법은 병렬 시뮬레이션의 성능 향상의 제약 요소인 동기 오버헤드 및 통신 오버헤드를 크게 감소시킨다. 이 두가지 중요한 예측정확도 향상 방법을 통하여 6개의 디자인들에 대한 예측기반 병렬 이벤트구동 게이트수준 타이밍 시뮬레이션이 기존 통상적 방식의 상용 병렬 멀티-코어 시뮬레이션에 비하여 약 5배의 시뮬레이션 성능이 향상됨을 확인할 수 있었다.

Keywords

References

  1. R. M. Fujimoto, "Parallel Discrete Event Simulation," Communication of the ACM, Vol.33, No.10, pp.30-53, Oct., 1990.
  2. D. M. Nicol, "Principles of Conservative Parallel Simulation," Proceedings of the 28th Winter Simulation Conference, pp.128-135, 1996.
  3. R. M. Fujimoto, "Time Warp on a Shared Memory Multiprocessor," Transactions of the Society for Computer Simulation, Vol.6, No.3, pp.211-239, Jul., 1989.
  4. L. Li and C. Tropper, "A design-driven partitioning algorithm for distributed Verilog simulation," in Proc. 20th International Workshop on Principles of Advanced and Distributed Simulation (PADS), pp.211-218, 2007.
  5. D. Chatterjee, A. DeOrio, and V. Bertacco, "Event-driven gate-level simulation with general purpose GPUs," Proc. of Design Automation Conference (DAC09), pp.557-562, Jun., 2009.
  6. IUS Simulator Usermanual, Cadence Design Systems [Internet], http://www.cadence.com.
  7. VCS Simulator Usermanual, Synopsys [Internet], http://www.synopsys.com.
  8. K. Chang and C. Browy, "Parallel Logic Simulation: Myth or Reality?" Computer, Vol.45, No.4, pp.67-73, Apr., 2012. https://doi.org/10.1109/MC.2011.385
  9. Jaehoon Han et al, "Predictive parallel event-driven HDL simulation with a new powerful prediction strategy," Proc. of Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.1-3, Mar., 2014.
  10. Yuhao Zhu, Bo Wang, and Yangdong Deng, "Massively Parallel Logic Simulation with GPUs," ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.16, No.3, pp.1-20, Jun., 2011.
  11. James Gross et al, "Multi-Level Parallelism for Time- and Cost-efficient Parallel Discrete-Event Simulation on GPUs," Proc. of 26th ACM/IEEE Workshop on Principles of Advanced and Distributed Simulation 2012 (PADS 2012), 2012.
  12. Gate-level Simulation Methodology, Whitepaper, Cadence Design Systems (www.cadence.com), 2013.
  13. Seiyang Yang, "A New Prediction-based Parallel Event-driven Logic Simulation," Journals of KIPS/ Computer and Communication Systems, Vol.4, No.3, pp.85-90, 2015.
  14. Doohwan Kwak and Seiyang Yang, "Checkpoint/resimulation Overhead Minimization with Sporadic Synchronization in Prediction-based Parallel Logic Simulation," Journals of KIPS/Computer and Communication Systems, Vol.4. No.5, pp.147-152, 2015.
  15. K. M. Chandy and J. Misra, "Distributed simulation: A case study in design and verification of distributed programs," IEEETrans.Softw. Engin. SE-5, Vol.5, pp.440-452, 1979.