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http://dx.doi.org/10.3745/KTCCS.2016.5.12.439

Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy  

Yang, Seiyang (부산대학교 정보컴퓨터공학부)
Publication Information
KIPS Transactions on Computer and Communication Systems / v.5, no.12, 2016 , pp. 439-446 More about this Journal
Abstract
In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction-based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.
Keywords
Verification; Event-Driven Logic Simulation; Parallel Logic Simulation;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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