• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39B no.1
• /
• pp.1-7
• /
• 2014

This paper proposes an efficient test wrapper design that reduces overall test time in multi-core SoC. After initial local wrapper solution sets for all the cores are determined using well-known Combine algorithm, proposed algorithm selects a dominant core which consumes the longest test time in multi-core SoC. Then, the wrapper characteristics in the number of TAM wires and the test time for other cores are adjusted based on test time of the dominant core. For some specific cores, the number of TAM wires can be reduced by increasing its test time for design space exploration purposes. These modified wrapper characteristics are added to the previous wrapper solution set. By expanding previous local wrapper solution set to global wrapper solution set, overall test time for Multi-core SoC can be reduced by an efficient test scheduler. Effectiveness of the proposed wrapper is verified on ITC'02 benchmark circuits using $B^*$-tree based test scheduler. Our experimental results show that the test time is reduced by an average of 4.7% when compared to that of employing previous wrappers.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.6
• /
• pp.99-104
• /
• 2013

Recently smart devices which combine traditional electronic devices and personal computers, such as smart phones and smart TV, have caught people's eyes from all over the world. A multi-media SoC platform which embeds not only a calculating processor but also an operating system could provide an user-customized environment of several types of communication methods to PC or Internet. In this paper, we describe a multi-functioning SoC platform with video, audio and other communicating protocols based on Core-A processor and AMBA buses. To verify the designed multi-media SoC platform, JPEG decoding and ADPCM encoding/decoding algorithms are applied on it and the final decoding results are confirmed by video monitors and audio speakers.

• Journal of IKEEE
• /
• v.16 no.4
• /
• pp.375-381
• /
• 2012

In this paper, we present an implementation of Viola-Jones algorithm in a multi-core SoC by using skin color information and a parallel processing method. In order to reduce unnecessary operations and improve the detection speed, we adopted a face detection algorithm based on skin color and deleted background image. The algorithm is functionally divided into several parts taking account of the size and the dependency so that the divided functions can be proceeded in parallel. Experiment results in SoC with built-in Cortex-A9 multi core show that it is about 1.8 times faster than the existing algorithm which is not divided.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.10a
• /
• pp.959-962
• /
• 2009

Recently, a multi-core system is studied for single terminal's operations on various service networks for mobile systems. Therefore, it is expected that mobile systems capable of supporting WCDMA, GSM, and WiBro would be developed. Mobile systems for supporting various service networks is able to be implemented on a single chipset via SoC(System on Chip) technology, thus a noble modem design proper for SoC technology is necessary. As those systems shall be operated at different frequency band with only a single terminal, a problem that a nonlinear characteristic according to the system and its frequency band is occurred. In this paper a noble modem design for multi-core systems is proposed and the nonlinear characteristics for those systems is analysed. The proposed modem design is based on OFDM(Orthogonal Frequency Division Multiplexing) and MC-CDMA scheme. And nonlinear characteristic analysis is done by PSD measurement.

• Journal of IKEEE
• /
• v.21 no.3
• /
• pp.260-263
• /
• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.

• Journal of IKEEE
• /
• v.21 no.3
• /
• pp.185-194
• /
• 2017

In this paper, a modular platform for wearable devices is proposed which can be easily assembled by exchanging functions according to various field and environment conditions. The proposed modular platform consists of a 32-bit RISC CPU, a 32-bit symmetric multi-core processor, and a 16-bit DSP. It also includes a plug & play features which can quickly respond to various environments. The sensing and communication modules are connected in the form of a chain. This work is implemented in a standard 130 nm CMOS technology and the proposed modular wearable platforms are verified with temperature and humidity sensors.

• Journal of computational fluids engineering
• /
• v.16 no.3
• /
• pp.95-103
• /
• 2011

In the block type VHTR core, there are inevitable gaps among core blocks for the installation and refueling of the fuel blocks. These gaps are called bypass gap and the bypass flow is defined as a coolant flows through the bypass gap. Distribution of core bypass flow varies according to the reactor operation since the graphite core blocks are deformed by the fast neutron irradiation and thermal expansion. Furthermore, the cross-flow through an interfacial gap between the stacked blocks causes flow mixing between the coolant holes and bypass gap, so that complicated flow distribution occurs in the core. Since the bypass flow affects core thermal margin and reactor efficiency, accurate prediction and evaluation of the core bypass flow are very important. In this regard, experimental and computational studies were carried out to evaluate the core bypass flow distribution. A multi-block experimental apparatus was constructed to measure flow and pressure distribution. Multi-block effect such as cross flow phenomenon was investigated in the experiment. The experimental data were used to validate a CFD model foranalysis of bypass flow characteristics in detail.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.3
• /
• pp.664-668
• /
• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• Journal of Advanced Navigation Technology
• /
• v.14 no.2
• /
• pp.213-219
• /
• 2010

Recently, a multi-core system is studied for single terminal's operations on various service networks for mobile systems. Therefore, it is expected that mobile systems capable of supporting WCDMA, MC-CDMA, CDMA and WiBro would be developed. Mobile systems for supporting various service networks is able to be implemented on a single chipset via SoC(System one Chip) technology, thus a noble modem design proper for SoC technology is necessary. For high speed data transmission of 4G mobile communication services, OFDM scheme has to be applied. But, an OFDM signal consists of a number of independently modulated subcarriers, and superposition of these subcarriers cause a problem that can give a large PAPR. In this paper, a noble modem design for 4G mobile communication services and PAPR reduction method for solving the PAPR problem are proposed.

• Transactions of Materials Processing
• /
• v.19 no.7
• /
• pp.411-415
• /
• 2010

A sandwich panel which is comprised of truss cores faced with solid face sheets is lightweight and multi-functional. So it is widely used to not only structural material but also heat transfer media in transportation field such as airplane, train and vessel. There are various core topologies such as pyramidal and tetrahedral truss, square honeycombs and kagome truss. The study focused on analytical approach to optimize compression and shear quality of the unit cell of PCM with pyramidal configuration. With various unit cell models which have the same core weight per unit area but different truss member angle, analytical solution for effective stress ($\bar{\sigma},\bar{\tau}$), peak stress ($\bar{\sigma}_{peak},\bar{\tau}_{peak}$) by yielding and buckling, relative density ($\bar{\rho}_c$) and effective stiffness ($\bar{E},\bar{G}$) have been computed and compared each other. With this approach, the most optimal core configuration was predicted. The result has become the efficient guidelines for the design of PCM core structure.