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http://dx.doi.org/10.7840/kics.2014.39B.1.1

A Test Wrapper Design to Reduce Test Time for Multi-Core SoC  

Kang, Woo-Jin (서강대학교 전자공학과 CAD & ES 연구실)
Hwang, Sun-Young (서강대학교 전자공학과 CAD & ES 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.39B, no.1, 2014 , pp. 1-7 More about this Journal
Abstract
This paper proposes an efficient test wrapper design that reduces overall test time in multi-core SoC. After initial local wrapper solution sets for all the cores are determined using well-known Combine algorithm, proposed algorithm selects a dominant core which consumes the longest test time in multi-core SoC. Then, the wrapper characteristics in the number of TAM wires and the test time for other cores are adjusted based on test time of the dominant core. For some specific cores, the number of TAM wires can be reduced by increasing its test time for design space exploration purposes. These modified wrapper characteristics are added to the previous wrapper solution set. By expanding previous local wrapper solution set to global wrapper solution set, overall test time for Multi-core SoC can be reduced by an efficient test scheduler. Effectiveness of the proposed wrapper is verified on ITC'02 benchmark circuits using $B^*$-tree based test scheduler. Our experimental results show that the test time is reduced by an average of 4.7% when compared to that of employing previous wrappers.
Keywords
Multi-Core SoC; Test Wrapper; TAM; Test Time; Test Scheduling;
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Times Cited By KSCI : 1  (Citation Analysis)
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