• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.43-48
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• 2002

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.5
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• pp.504-514
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• 2014

An MMIC multi-function chip with a low DC power consumption for an X-band active phased array radar system has been designed and fabricated using a 0.5 ${\mu}m$ GaAs p-HEMT commercial process. The multi-function chip provides several functions: 6-bit phase shifting, 6-bit attenuation, transmit/receive switching, and signal amplification. The fabricated multi-function chip with a compact size of $16mm^2(4mm{\times}4mm)$ exhibits a gain of 10 dB and a P1dB of 14 dBm from 7 GHz to 11 GHz with a DC low power consumption of only 0.6 W. The RMS(Root Mean Square) errors for the 64 states of the 6-bit phase shift and attenuation were measured to $3^{\circ}$ and 0.6 dB, respectively over the frequency.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• ETRI Journal
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• v.27 no.5
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.2
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• pp.142-147
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• 2009

Conventional HP(high pressure) sodium or Metal-halide lamps have a life span of around one year requiring at least annual replacement and maintenance. High Power LED lights require no regular maintenance further increasing savings on replacement bulbs, access equipment and labour costs. New installations benefit from a substantial reduction in the cost of expensive heavy duty cable required for sodium lighting. Especially, LED light can achieve variable color temperature, high functional performance in the field of street light. There are two main method to achieve variable color temperature function of the street light. one method is using RGB multi-chip LED, the other is using Orange-White LED method. In this paper, it was compare RGB Multi-chip LED with white-orange LED for there characteristics performance.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.3 no.2
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• pp.63-68
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• 1989

This paper discussed the Multi-PAM inverter for static power supply design. The controller part composed of one-chip microcomputer obtained control pattern simply. The configuration of termination part was composed of double bridge inverter and three-phase, three-winding transformer. The output waveforms using a controller and transformers synthesized the multi-PAM wave form by a voltage level of 22 steps per one-cycle. The output waveforms using the Low Pass Filter approximated to the sine wave.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.711-712
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• 2009

MCP 기술을 이용한 반도체 칩에서 문제가 되는 방열문제를 해결하기 위한 방법으로 열전 냉각 소자를 이용하여 열을 방출 시키는 방법에 관하여 연구를 수행하였다. 시뮬레이션을 통하여 열전 소자가 작동할 때, 흡수하는 열량을 계산할 수 있었으며, 열전 소자의 냉각 성능도 평가 할 수 있었다. 이러한 열 해석 및 열전 해석을 통하여 적층 구조의 MCP 모듈을 위한 열 설계 및 효율적 냉각을 가능하게 할 수 있을 것이다.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.7-12
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• 2006

The multi-functional one-chip sensor has been fabricated to reduce output variation under various water environment. There were a temperature sensor, a piezoresistive type pressure sensor, and a electrode type conductivity sensor in the fabricated one-chip sensor. This sensor was measured water depth in the range of $0{\sim}180cm$, temperature in the range of $0{\sim}50^{\circ}C$, and salinity in the range of 0 $0wt%{\sim}5wt%$, respectively. Since the change of water depth in solution environment depends on various factors such as salinity, latitude, temperature, and atmospheric pressure, the water depth sensor is needed to be compensated. We tried to compensate the salinity and temperature dependence for the pressure in water by using lookup-table method.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.35-40
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• 2000

MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.