1 |
'AMBA Specification,'http://www.arm.com/products/solutions/AMBA_Spec.html
|
2 |
'AMBA AHB BusMatrix Specification,' Document Number ARM DUI 0092C
|
3 |
'The CoreConnect Bus Architecture,' http://www3.ibm.com/ chips/products/coreconnect
|
4 |
'Wishbone,' http://www.opencores.org
|
5 |
'SiliconBackplaneTM III MicroNetwork IP, 'http:// www.sonicsinc.com/sonics/products/siliconbackplaneIII/
|
6 |
Sung-Ho Moon; Dan Keun Sung 'Highperformance variable-length packet scheduling algorithm for IP traffic,' Global Telecommunications Conference, GLOBECOM '01. IEEE, Vol. 4, Nov. 2001 Page(s):2666-2670
DOI
|
7 |
K. Lahiri, A. Raghunathan, G, Lakshminaray- ana, 'LOTTERYBUS : A new high-performance communication architecture for system-on-chip designs,' in Proc. Design Automation Conf. pp 15-20, 2001
DOI
|
8 |
Kyeong Keol Ryu, Eung Shin, V.J. Mooney, 'A comparison of five different multiprocessor SoC bus architectures,' in Proc. of Euromicro Symposium on Warsaw Poland, Digital Systems, Design, pp. 202-209, Sept. 2001
DOI
|