• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.83-92
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• 2012

This paper suggests an improved method of grouping minterms based on the Decimal-Valued Matrix (DVM) method. The DVM is a novel approach to Boolean logic minimization method which was recently developed by this author. Using the minterm-based matrix layout, the method captures binary number based minterm differences in decimal number form. As a result, combinable minterms can be visually identified. Furthermore, they can be systematically processed in finding a minimized Boolean expression. Although this new matrix based approach is visual-based, the suggested method in symmetric grouping cell values can become rather messy in some cases. To alleviate this problem, the enhanced DVM method that is based on multi-level groupings of combinable minterms is presented in this paper. Overall, since the method described here provides a concise visualization of minterm groupings, it facilitates a user with more options to explore different combinable minterm groups for a given Boolean logic minimization problem.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.2
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• pp.25-30
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• 1985

This paper proposes an algorithm to simplify Boolean functions into near minimal sum-of-products for Programmable Logic Arrays. In contrast to the conventional procedures, where the execution time depends on the number of variables, the execution time by this procedure depends on the degree of consensus of base minterms. Thus as the number of variables is increased, the difference of CPU time becomes larger using this new Procedure than using other procedures and consequently the executable range of input function increasing. The algorithm has been implemented on CYEER 170-740 and it's results were compared with those using Arvalo's algorithm.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.5
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• pp.9-19
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• 2011

In many instances a concise form of logic is often required for building today's complex systems. The method described in this paper can be used for a wide range of industrial applications that requires Boolean type of logic minimization. Unlike some of the previous logic minimization methods, the proposed method can be used to better gain insights into the logic minimization process. Based on the decimal valued matrix, the method described here can be used to find an exact minimized solution for a given Boolean function. It is a visual based method that primarily relies on grouping the cell values within the matrix. At the same time, the method is systematic to the extent that it can also be computerized. Constructing the matrix to visualize a logic minimization problem should be relatively easy for the most part, particularly if the computer-generated graphs are accompanied.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.525-528
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• 1988

In this paper, a new multi-output logic minimization algorithm is presented. A base minterm is selected in the given function and the prime implicant is obtained by expanding it in the order of the expansion set that is decided by heuristic method. Input-oriented expansion procedure is used to reduce fan-in and fan-out number. To show the effectiveness of this algorithm, comparative run time with other minimization algorithm is given.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.1
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• pp.25-35
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• 2013

Automatically deriving only individual don't-care minterms that can effectively reduce a Boolean logic expressions are being investigated. Don't-care conditions play an important role in optimizing logic design. The type of unknown don't-care minterms that can always reduce the number of product terms in Boolean expression are referred as single hypothetical don't-care (S-HDC) minterms. This paper describes the Quasi Quine-McCluskey method that systematically derives S-HDC minterms. For the most part, this method is similar to the original Quine-McCluskey method in deriving the prime implicants. However, the Quasi Quine-McCluskey method further derives S-HDC minterms by applying so-called a combinatorial comparison operation. Upon completion of the procedure, the designer can review generated S-HDC minterms to test its appropriateness for a particular application.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.51-57
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• 1980

Any switching function can be constructed with universal building block of MAND gate. Threelevel AND-NOT logic networks with only true inputs are called TANT networks. Systematic approach to TANT minimization starts from the UF type minterm with the smallest subscript and ends when UF type minterms are all covered. Optinal PEI is composed of CPPI or EPPi without C-C table. The algorithm in this work is usful in solving TANT optimization porblem of four or five variables by hand solution. When variable are six or more, it is required to be solved by computer, A CAD software package of this algorithm with FORTRAN IV language is made to solve such problems.

• Journal of KIISE:Software and Applications
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• v.28 no.9
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• pp.662-668
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• 2001

Since the problem of disproving a tautology is as hard as the problem of proving it, no polynomial time algorithm for falsification(or testing invalidity) is feasible. Previous algorithms are mostly based on either divide-and-conquer or graph representation. Most of them demonstrated satisfactory results on a variety of input under certain constraints. However, they have experienced difficulties dealing with big input. We propose a new falsification algorithm using a Merge Rule to produce a counterexample by constructing a minterm which is not satisfied by an input expression in DNF(Disjunctive Normal Form). We also show that the algorithm is consistent and sound. The algorithm is based on a greedy method which would seek to maximize the number or terms falsified by the assignment made at each step of the falsification process. Empirical results show practical performance on big input to falsify randomized nontautological problem instances, consuming O(nm$^2$) time, where n is the number of variables and m is number of terms.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.95-102
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• 2015

This paper proposes a simple algorithm for circuit minimization. There are currently two effective heuristics for circuit minimization, namely manual Karnaugh maps and computable Quine-McCluskey algorithm. The latter, however, has a major defect: the runtime and memory required grow $3^n/n$ times for every increase in the number of variables n. The proposed algorithm, however, extracts the prime implicants (PI) that cover minterms of a given Boolean function by deriving an implicants table based on frequency. From a set of the extracted prime implicants, the algorithm then eliminates redundant PIs again based on frequency. The proposed algorithm is therefore capable of minimizing circuits polynomial time when faced with an increase in n. When applied to various 3-variable and 4-variable cases, it has proved to swiftly and accurately obtain the optimal solutions.