1 |
V. Kabanets and J. Y. Cai, "Circuit Minimization Problem," Proceedings of 32nd Symposiumon Theory of Computing, Portland, Oregon, USA, pp. 73-79, Jun. 2000.
|
2 |
M. Karnaugh, "The Map Method for Synthesis of Combinational Logic Circuits," Transactions of the American Institute of Electrical Engineers, part I, Vol. 72, No. 9, pp. 593-599, Nov. 1953.
|
3 |
N. Sarkar, K. Petrus, and H. Hossain, "Software Implementation of theQuine-McCluskey Algorithmfor Logic GateMinimisation," Proceedings of the NACCQ, pp. 375-378, Napier, New Zealand, Jul, 2001.
|
4 |
R. K. Brayton, G. D.Hachtel, C.McMullen, andA. L. Sangiovanni-Vincentelli, "LogicMinimizationAlgorithms for VLSI Synthesis," Springer, 1984.
|
5 |
N. V. Vinodchandran, "Nondeterministic Circuit Minimization Problemand Derandomizing Arthur-MerlinGames," International Journal of Foundations of Computer Science, Vol. 16, No. 6, pp.1297-1308, Dec. 2005.
DOI
ScienceOn
|
6 |
R. Siggh, A. Arora, G. Singh, and J.Malhotra, "Circuit Minimization in VLSI Using PSO&GA Algorithms," International Journal of Engineering Trends and Technology, Vol. 3, No. 1, pp. 43-46, Feb. 2012.
|
7 |
M. Morrison and N. Ranganathan, "A Novel Optimization Method for Reversible Logic Circuit Minimization," IEEE Computer Society Annual Symposiumon VLSI (ISVLSI), pp. 182-187, Aug. 2013.
|
8 |
S. R. Petrick, "ADirect Termination of the Irredundant Forms of a Boolean Function fromthe Set of Prime Implicants," Technical Report AFCRC-TR-56-110, Air Force Cambridge Res. Center, Cambridge, MA, USA, 1956.
|
9 |
T.H. Cormen, C. E. Leiserson, R. L. Rivest, L. Ronald, andC. Stein, "Introduction toAlgorithms,"McGraw-Hill, pp. 1033-1038, 2001.
|
10 |
S. U. Lee, "An ImprovedQuine-McCluskey Algorithm for CircuitMinimization," Journal of KSCI, Vol. 19, No. 3, pp. 109-117, Mar. 2014.
|