• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.159-162
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• 2009

The necessity of radiation dosimeter with precise measurement of radiation dose is increased and required in the field of spacecraft, radiotheraphy hospital, atomic plant facility, etc. where radiation exists. Until now, a low power commercial metal-oxide semiconductor(MOS) transistor has been tested as a gamma radiation dosimeter. The measurement error between the actual value and the measurement one can occur since the MOSFET(MOS field-effect transistor) dosimeter, which is now being used, has two gates with same width. The measurement value of dosimeter depends on the variation of threshold voltage, which can be affected by the environment such as temperature. In this paper, a radiation dosimeter having a pair of MOSFET is designed in the same silicon substrate, in which each of the MOSFETs is operable in a bias mode and a test mode. It can measure the radiation dose by the difference between the threshold voltages regardless of the variation of temperature.

• 한국정보통신학회논문지
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• 제20권10호
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• pp.1927-1934
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• 2016

본 논문에서는 일반적인 실리콘 기반 n-MOSFET(n-type Metal Oxide Semiconductor Field Effect Transistor)의 절연 산화막 계면에서 방사선으로부터 유발되는 누설전류 경로를 차단하기 위하여 I형 게이트 n-MOSEFT 구조를 제안하였다. I형 게이트 n-MOSFET 구조는 상용 0.18um CMOS(Complementary Metal Oxide Semiconductor) 공정에서 레이아웃 변형 기법을 이용하여 설계되었으며, ELT(Enclosed Layout Transistor)와 DGA(Dummy Gate-Assisted) n-MOSFET와 같은 레이아웃 변형 기법을 사용한 기존 내방사선 전자소자의 구조적 단점을 개선하였다. 따라서, 기존 구조와 비교하여 반도체 칩 제작에서 회로 설계의 확장성을 확보할 수 있다. 또한, 내방사선 특성 검증을 위하여 TCAD 3D(Technology Computer Aided Design 3-dimension) tool을 사용하여 모델링과 모의실험을 수행하였고, 그 결과 I형 게이트 n-MOSFET 구조의 내방사선 특성을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.268-268
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• 2016

Chemical sensors have attracted much attention due to their various applications such as agriculture product, cosmetic and pharmaceutical components and clinical control. A conventional chemical and biological sensor is consists of fluorescent dye, optical light sources, and photodetector to quantify the extent of concentration. Such complicated system leads to rising cost and slow response time. Until now, the most contemporary thin film transistors (TFTs) are used in the field of flat panel display technology for switching device. Some papers have reported that an interesting alternative to flat panel display technology is chemical sensor technology. Recent advances in chemical detection study for using TFTs, benefits from overwhelming progress made in organic thin film transistors (OTFTs) electronic, have been studied alternative to current optical detection system. However numerous problems still remain especially the long-term stability and lack of reliability. On the other hand, the utilization of metal oxide transistor technology in chemical sensors is substantially promising owing to many advantages such as outstanding electrical performance, flexible device, and transparency. The top-gate structure transistor indicated long-term atmosphere stability and reliability because insulator layer is deposited on the top of semiconductor layer, as an effective mechanical and chemical protection. We report on the fabrication of InGaZnO TFTs with silver nanowire as the top gate electrode for the aim of chemical materials detection by monitoring change of electrical properties. We demonstrated that the improved sensitivity characteristics are related to the employment of a unique combination of nano materials. The silver nanowire top-gate InGaZnO TFTs used in this study features the following advantages: i) high sensitivity, ii) long-term stability in atmosphere and buffer solution iii) no necessary additional electrode and iv) simple fabrication process by spray.

• 대한전자공학회논문지SD
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• 제47권10호
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• pp.14-22
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• 2010

기존의 n-type metal-oxide-semiconductor field effect transistor(NMOSFET)은 $n^+/p^{(+)}/n^+$ type의 이온 주입을 통하여 소스/채널/드레인 영역을 형성하게 된다. 30 nm 이하의 채널 길이를 갖는 초미세 소자를 제작함에 있어서 설계한 유효 채널 길이를 정확하게 얻기 위해서는 주입된 이온들을 완전히 activation하여 전류 수준을 향상시키면서도 diffusion을 최소화하기 위해 낮은 thermal budget을 갖도록 공정을 설계해야 한다. 실제 공정에서의 process margin을 완화할 수 있도록 오히려 p-type 채널을 형성하져 않으면서도 기존의 NMOSFET의 동작을 온전히 구현할 수 있는 junctionless(JL) MOSFET이 연구중이다. 본 논문에서는 3차원 소자 시뮬레이션을 통하여 silicon nanowire(SNW) 구조에 접목시킨 JL MOSFET을 최적 설계하고 그러한 조건의 소자에 대하여 conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) 등의 기본적인 고주파 특성을 분석한다. 채널 길이는 30 nm이며 설계 변수는 채널 도핑 농도와 채널 SNW의 반지름이다. 최적 설계된 JL SNW NMOSFET에 대하여 동작 조건($V_{GS}$ = $V_{DS}$ = 1.0 V)에서 각각 367.5 GHz, 602.5 GHz의 $f_T$, $f_{max}$를 얻을 수 있었다.

• Journal of information and communication convergence engineering
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• 제11권4호
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• pp.288-292
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• 2013

In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage ($V_{th}$) adjustment using a carbon implant significantly improves the $V_{th}$ mismatch performance in a thick (3.3-V) n-MOS transistor. It has been reported that a bad mismatch occurs particularly in the case of 0.11-${\mu}m$ $V_{th}$ node technology. This paper investigates a carbon implant process as a promising candidate for the optimal $V_{th}$ roll-off curve. The carbon implant makes the $V_{th}$ roll-off curve perfectly flat, which is explained in detail. Further, the mechanism of hot carrier injection lifetime degradation by the carbon implant is investigated, and new process integration involving the addition of a nitrogen implant in the lightly doped drain process is offered as its solution. This paper presents the critical side effects, such as Isub increases and device performance shifts caused by the carbon implant and suggests an efficient method to avoid these issues.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.206.2-206.2
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• 2015

최근 비정질 산화물 반도체 thin film transistor(TFT)는 차세대 투명 디스플레이로 많은 관심을 받고 있으며 활발한 연구가 진행되고 있다. 산화물 반도체 TFT는 기존의 비정질 실리콘 반도체에 비하여 큰 on/off 전류비, 높은 이동도 그리고 낮은 구동전압으로 인하여 차세대 투명 디스플레이 산업에 적용 가능하다는 장점이 있다. 한편 기존의 sputter나 evaporator를 이용한 증착 방식은 우수한 막의 특성에도 불구하고 많은 시간과 제작비용이 든다는 단점을 가지고 있다. 따라서 본 연구에서는 별도의 고진공 시스템이 필요하지 않을 뿐만 아니라 대면적화에도 유리한 용액공정 방식을 이용하여 박막 트렌지스터를 제작하였으며 thermal 열처리와 microwave 열처리 방식에 따른 전기적 특성을 비교 및 분석하고 각 열처리 방식의 열처리 온도 및 조건을 최적화 하였다. 제작된 박막 트렌지스터는 p-type bulk silicon 위에 산화막이 100 nm 형성된 기판에 spin coater을 이용하여 Al-Zn-Sn-O 박막을 형성하였다. 연속해서 photolithography 공정과 BOE (30:1) 습식 식각 과정을 이용해 활성화 영역을 형성하여 소자를 제작하였다. 제작 된 소자는 Pseudo-MOS FET구조이며, 프로브 탐침을 증착 된 채널층 표면에 직접 접촉시켜 소스와 드레인 역할을 대체하여 동작시킬 수 있어 전기적 특성평가가 용이하다는 장점을 가지고 있다. 그 결과, microwave를 통해 열처리한 소자는 100oC 이하의 낮은 열처리 온도에도 불구하고 furnace를 이용하여 열처리한 소자와 비교하여 subthreshold swing(SS), Ion/off ratio, field-effectmobility 등이 개선되는 것을 확인하였다. 따라서, microwave 열처리 공정은 향후 저온 공정을 요구하는 MOSFET 제작 시의 훌륭한 대안으로 사용 될 것으로 기대된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.657-663
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• 2016

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.270-275
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• 2012

Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

• 정보저장시스템학회:학술대회논문집
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• 정보저장시스템학회 2005년도 추계학술대회 논문집
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• pp.56-58
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• 2005

To illustrate an application of the field effect transistor (FET) structure, this study suggests a new cantilever, using atomic force microscopy (AFM), for sensing surface potentials in nanoscale. A combination of the micro-electromechanical system technique for surface and bulk and the complementary metal oxide semiconductor process has been employed to fabricate the cantilever with a silicon-on-insulator (SOI) wafer. After the implantation of a high-ion dose, thermal annealing was used to control the channel length between the source and the drain. The basic principle of this cantilever is similar to the FET without a gate electrode.

• 전력전자학회논문지
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• 제25권5호
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• pp.350-357
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• 2020

This study presents the design of an 18 kW two-phase interleaved buck converter that uses a coupled inductor for an electric vehicle rapid charger. The designs of a two-phase coupled inductor for current ripple and physical size reduction and a two-phase interleaved buck converter based on silicon carbide metal - oxide - semiconductor field-effect transistor for high efficiency were described in detail. The operating principle of the two-phase interleaved buck converter was analyzed, and the coupled inductor was investigated using a magnetized equivalent circuit. Simulation and experiments were conducted to verify the validity of the proposed two-phase interleaved buck converter, and the theoretical design method and experimental results were confirmed.