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Optimum Design of Junctionless MOSFET Based on Silicon Nanowire Structure and Analysis on Basic RF Characteristics  

Cha, Seong-Jae (School of Electrical Engineering and Computer Science, Seoul National University)
Kim, Kyung-Rok (School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology)
Park, Byung-Gook (School of Electrical Engineering and Computer Science, Seoul National University)
Rang, In-Man (School of Electronics Engineering, Kyungpook National University)
Publication Information
Abstract
The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).
Keywords
thermal budget; junctionless MOSFET; process margin; silicon nanowire; 3-D device simulation;
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Times Cited By KSCI : 4  (Citation Analysis)
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