• Title/Summary/Keyword: Metal-Oxide-Semiconductor Field-Effect transistor (MOSFET)

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Properties of CNT field effect transistors using top gate electrodes (탑 게이트 탄소나노튜브 트랜지스터 특성 연구)

  • Park, Yong-Wook;Yoon, Seok-Jin
    • Journal of Sensor Science and Technology
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    • v.16 no.4
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    • pp.313-318
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    • 2007
  • Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

Effects of Ti and TiN Capping Layers on Cobalt-silicided MOS Device Characteristics in Embedded DRAM and Logic

  • Kim, Jong-Chae;Kim, Yeong-Cheol;Choy, Jun-Ho
    • Journal of the Korean Ceramic Society
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    • v.38 no.9
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    • pp.782-786
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    • 2001
  • Cobalt silicide has been employed to Embedded DRAM (Dynamic Random Access Memory) and Logic (EDL) as contact material to improve its speed. We have investigated the influences of Ti and TiN capping layers on cobalt-silicided Complementary Metal-Oxide-Semiconductor (CMOS) device characteristics. TiN capping layer is shown to be superior to Ti capping layer with respect to high thermal stability and the current driving capability of pMOSFETs. Secondary Ion Mass Spectrometry (SIMS) showed that the Ti capping layer could not prevent the out-diffusion of boron dopants. The resulting operating current of MOS devices with Ti capping layer was degraded by more than 10%, compared with those with TiN.

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Test-bed of Total Ionizing Dose (TID) Test by Cosmic Rays for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (금속-산화막 반도체 전계효과 트랜지스터의 우주방사선에 의한 총이온화선량 시험을 위한 테스트 베드)

  • Sin, Gu-Hwan;Yu, Gwang-Seon;Gang, Gyeong-In;Kim, Hyeong-Myeong;Jeong, Seong-In
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.34 no.11
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    • pp.84-91
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    • 2006
  • Recently, all the electrical parts for satellite application are required more strong against cosmic rays, because spacecraft's life time and function are depending on the their conditions. Also, a TID effect test was undertaken with units and/or subsystems which are already assembled on the PCB in past time. However, it is very hard to know and analyze that some abnormal states are appeared after launch. Moreover, it is necessary to perform a test of TID effects based on the parts level for preparing preliminary data in cosmic rays. Therefore, this paper presents a test-bed to perform a TID effect test of Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) which is a fundamental element for electronics.

Simulation Studies on the Super-junction MOSFET fabricated using SiGe epitaxial process (SiGe 에피 공정기술을 이용하여 제작된 초 접합 금속-산화막 반도체 전계 효과 트랜지스터의 시뮬레이션 연구)

  • Lee, Hoon-Ki;Park, Yang-Kyu;Shim, Kyu-Hwan;Choi, Chel-Jong
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.3
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    • pp.45-50
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    • 2014
  • In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

A Study on 600 V Super Junction Power MOSFET Optimization and Characterization Using the Deep Trench Filling (Deep Trench Filling 기술을 적용한 600 V급 Super Junction Power MOSFET의 최적화 특성에 관한 연구)

  • Lee, Jung-Hoon;Jung, Eun-Sik;Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.4
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    • pp.270-275
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    • 2012
  • Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

Comparison on Micro-Tec and TCAD simulators for device simulation (소자 시뮬레이션을 위한 Micro-Tec과 TCAD의 비교 분석)

  • 심성택;장광균;정정수;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.05a
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    • pp.321-324
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    • 2001
  • The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased packing density. This paper has compared Micro-Tec with ISE-TCAD. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths 180nm. We have presented MOSF ET's characteristics such as I-V characteristic, electric field. and compared with Micro-Tec and ISE-TCAD.

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Development of 900 V Class MOSFET for Industrial Power Modules (산업 파워 모듈용 900 V MOSFET 개발)

  • Chung, Hunsuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.33 no.2
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    • pp.109-113
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    • 2020
  • A power device is a component used as a switch or rectifier in power electronics to control high voltages. Consequently, power devices are used to improve the efficiency of electric-vehicle (EV) chargers, new energy generators, welders, and switched-mode power supplies (SMPS). Power device designs, which require high voltage, high efficiency, and high reliability, are typically based on MOSFET (metal-oxide-semiconductor field-effect transistor) and IGBT (insulated-gate bipolar transistor) structures. As a unipolar device, a MOSFET has the advantage of relatively fast switching and low tail current at turn-off compared to IGBT-based devices, which are built on bipolar structures. A superjunction structure adds a p-base region to allow a higher yield voltage due to lower RDS (on) and field dispersion than previous p-base components, significantly reducing the total gate charge. To verify the basic characteristics of the superjunction, we worked with a planar type MOSFET and Synopsys' process simulation T-CAD tool. A basic structure of the superjunction MOSFET was produced and its changing electrical characteristics, tested under a number of environmental variables, were analyzed.

Implementation of DC/DC Power Buck Converter Controlled by Stable PWM (안정된 PWM 제어 DC/DC 전력 강압 컨버터 구현)

  • Lho, Young-Hwan
    • Journal of Institute of Control, Robotics and Systems
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    • v.18 no.4
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    • pp.371-374
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    • 2012
  • DC/DC switching power converters produce DC output voltages from different stable DC input sources regulated by a bi-polar transistor. The converters can be used in regenerative braking of DC motors to return energy back in the supply, resulting in energy savings for the systems containing frequent stops. The voltage mode DC/DC converter is composed of a PWM (Pulse Width Modulation) controller, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an inductor, and capacitors, etc. PWM is applied to control and regulate the total output voltage. It is shown that the output of DC/DC converter depends on the variation of threshold voltage at MOSFET and the variation of pulse width. In the PWM operation, the missing pulses, the changes in pulse width, and a change in the period of the output waveform are studied by SPICE (Simulation Program with Integrated Circuit Emphasis) and experiments.

Electrothermal Analysis for Super-Junction TMOSFET with Temperature Sensor

  • Lho, Young Hwan;Yang, Yil-Suk
    • ETRI Journal
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    • v.37 no.5
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    • pp.951-960
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    • 2015
  • For a conventional power metal-oxide-semiconductor field-effect transistor (MOSFET), there is a trade-off between specific on-state resistance and breakdown voltage. To overcome this trade-off, a super-junction trench MOSFET (TMOSFET) structure is suggested; within this structure, the ability to sense the temperature distribution of the TMOSFET is very important since heat is generated in the junction area, thus affecting its reliability. Generally, there are two types of temperature-sensing structures-diode and resistive. In this paper, a diode-type temperature-sensing structure for a TMOSFET is designed for a brushless direct current motor with on-resistance of $96m{\Omega}{\cdot}mm^2$. The temperature distribution for an ultra-low on-resistance power MOSFET has been analyzed for various bonding schemes. The multi-bonding and stripe bonding cases show a maximum temperature that is lower than that for the single-bonding case. It is shown that the metal resistance at the source area is non-negligible and should therefore be considered depending on the application for current driving capability.

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

  • Sahu, P.K.;Mohapatra, S.K.;Pradhan, K.P.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.6
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    • pp.647-654
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    • 2013
  • The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.