• 센서학회지
• /
• 제16권4호
• /
• pp.313-318
• /
• 2007

Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

• 한국세라믹학회지
• /
• 제38권9호
• /
• pp.782-786
• /
• 2001

Cobalt silicide has been employed to Embedded DRAM (Dynamic Random Access Memory) and Logic (EDL) as contact material to improve its speed. We have investigated the influences of Ti and TiN capping layers on cobalt-silicided Complementary Metal-Oxide-Semiconductor (CMOS) device characteristics. TiN capping layer is shown to be superior to Ti capping layer with respect to high thermal stability and the current driving capability of pMOSFETs. Secondary Ion Mass Spectrometry (SIMS) showed that the Ti capping layer could not prevent the out-diffusion of boron dopants. The resulting operating current of MOS devices with Ti capping layer was degraded by more than 10%, compared with those with TiN.

• 한국항공우주학회지
• /
• 제34권11호
• /
• pp.84-91
• /
• 2006

최근에 인공위성용 전자소자는 우주방사선에 좀 더 강한 소자를 요구되어진다. 왜냐하면, 인공위성의 수명과 기능은 우주방사선으로부터 영향을 받기 때문이다. 또한, 과거에는 부품단위의 우주방사선 시험을 수행하지 않고 유닛 또는 서브시스템 단위의 우주방사선 시험을 수행하였다. 게다가, 발사된 인공위성이 작동오류 상태에 있을 때 그 이유를 분석하기에는 그다지 쉬운 일은 아니다. 따라서, 발사 전 부품 단위 우주방사선 시험을 수행하여 주요 소자에 대한 우주방사선에 의한 영향을 분석 할 필요가 있으며, 지상에서 데이터를 확보할 필요가 있다. 그러므로, 본 논문에서는 모든 전자소자의 기본이라 할 수 있는 금속-산화막 반도체 전계효과 트랜지스터의 총이온화선량에 대한 영향 시험을 수행하기 위한 테스트 베드를 제안한다.

• 반도체디스플레이기술학회지
• /
• 제13권3호
• /
• pp.45-50
• /
• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• 한국전기전자재료학회논문지
• /
• 제25권4호
• /
• pp.270-275
• /
• 2012

Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2001년도 춘계종합학술대회
• /
• pp.321-324
• /
• 2001

MOSFET는 전력감소, 도핑농도 증가, 캐리어 속도 증가를 위해서 많은 변화를 가져왔다. 이러한 변화를 받아들이기 위해서, 채널의 길이와 공급전압이 감소해야만했으며, 그것으로 인해 소자가 더욱 작아지게 되었다. 본 논문에서는 이러한 변화를 두 가지의 시뮬레이터를 사용하여 비교 분석하였다. 사용되어진 시뮬레이터는 Micro-Tec과 ISE-TCAD이며, 본 논문에서 LDD(lightly-doped drain) MOSFET에 관하여 시뮬레이션 하였다. 게이트 길이는 180nm를 기준으로 MOSFET의 특성과 전계를 비교 분석하였다.

• 한국전기전자재료학회논문지
• /
• 제33권2호
• /
• pp.109-113
• /
• 2020

A power device is a component used as a switch or rectifier in power electronics to control high voltages. Consequently, power devices are used to improve the efficiency of electric-vehicle (EV) chargers, new energy generators, welders, and switched-mode power supplies (SMPS). Power device designs, which require high voltage, high efficiency, and high reliability, are typically based on MOSFET (metal-oxide-semiconductor field-effect transistor) and IGBT (insulated-gate bipolar transistor) structures. As a unipolar device, a MOSFET has the advantage of relatively fast switching and low tail current at turn-off compared to IGBT-based devices, which are built on bipolar structures. A superjunction structure adds a p-base region to allow a higher yield voltage due to lower R_DS (on) and field dispersion than previous p-base components, significantly reducing the total gate charge. To verify the basic characteristics of the superjunction, we worked with a planar type MOSFET and Synopsys' process simulation T-CAD tool. A basic structure of the superjunction MOSFET was produced and its changing electrical characteristics, tested under a number of environmental variables, were analyzed.

• 제어로봇시스템학회논문지
• /
• 제18권4호
• /
• pp.371-374
• /
• 2012

DC/DC switching power converters produce DC output voltages from different stable DC input sources regulated by a bi-polar transistor. The converters can be used in regenerative braking of DC motors to return energy back in the supply, resulting in energy savings for the systems containing frequent stops. The voltage mode DC/DC converter is composed of a PWM (Pulse Width Modulation) controller, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an inductor, and capacitors, etc. PWM is applied to control and regulate the total output voltage. It is shown that the output of DC/DC converter depends on the variation of threshold voltage at MOSFET and the variation of pulse width. In the PWM operation, the missing pulses, the changes in pulse width, and a change in the period of the output waveform are studied by SPICE (Simulation Program with Integrated Circuit Emphasis) and experiments.

• ETRI Journal
• /
• 제37권5호
• /
• pp.951-960
• /
• 2015

For a conventional power metal-oxide-semiconductor field-effect transistor (MOSFET), there is a trade-off between specific on-state resistance and breakdown voltage. To overcome this trade-off, a super-junction trench MOSFET (TMOSFET) structure is suggested; within this structure, the ability to sense the temperature distribution of the TMOSFET is very important since heat is generated in the junction area, thus affecting its reliability. Generally, there are two types of temperature-sensing structures-diode and resistive. In this paper, a diode-type temperature-sensing structure for a TMOSFET is designed for a brushless direct current motor with on-resistance of $96m{\Omega}{\cdot}mm^2$. The temperature distribution for an ultra-low on-resistance power MOSFET has been analyzed for various bonding schemes. The multi-bonding and stripe bonding cases show a maximum temperature that is lower than that for the single-bonding case. It is shown that the metal resistance at the source area is non-negligible and should therefore be considered depending on the application for current driving capability.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권6호
• /
• pp.647-654
• /
• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.