• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.159-160
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• 2002

본 논문에서는 반도체 응용부문 중 그 활용도가 높은 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)의 새로운 구조를 제안하였다. 제안한 소자를 가지고 전자회로의 구성할 때 인접 디바이스들과 연계되어 발생되는 래치 업(latch-up)을 근본적으로 제거하고, 개별소자의 완전한 절연을 실현하였으며 누설전류 또한 제거된다. 이는 SOI기판 위에 벌크실리콘 공정을 이용하여 구현된다. 즉, 소자 양옆의 트랜치 웰(Trench-well)과 SOI 기판의 절연층으로 소자의 독립성을 지켜준다. 또한 게이트 절연층을 트랜치 구조로 기존 MOS구조의 채널 부분에 위치시키고 드레인과 소스를 위치시켜 자연적으로 자기정렬이 되어진다. 이와 같은 과정으로 게이트-소스, 게이트-드레인 기생 커패시터의 효과를 현저히 줄일 수 있다.

• Journal of the Korean Society for Railway
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• v.13 no.5
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• pp.504-508
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• 2010

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide under the environment that radiation exists. The energy loss will be also studied as the inductance values are changed. In this paper, the electrical characteristics are simulated by SPICE, and compared for variation of inductance and threshold voltage based on IGBT.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.146-146
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• 2010

일반적인 MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor)은 소스와 드레인의 형성을 위해서 불순물을 주입하고 고온의 열처리 과정을 거치게 된다. 이러한 고온의 열처리 과정 때문에 녹는점이 낮은 메탈게이트와 게이트 절연막으로의 high-k 물질의 사용에 제한을 받게된다. 이와 같은 문제점을 보완하기 위해서 소스와 드레인 영역에 불순물 주입공정 대신에 금속접합을 이용한 Schottky Barrier Tunnel Transistor (SBTT)가 제안되었다. SBTT는 $500^{\circ}C$ 이하의 저온에서 불순물 도핑없이 소스와 드레인의 형성이 가능하며 실리콘에 비해서 수십~수백배 낮은 면저항을 가지며, 단채널 효과를 효율적으로 제어할 수 있는 장점이 있다. 또한 고온공정에 치명적인 단점을 가지고 있는 high-k 물질의 적용 또한 가능케한다. 본 연구에서는 p-type SOI (Silicon-On-Insulator) 기판을 이용하여 Pt-silicide 소스와 드레인을 형성하고 전기적인 특성을 분석하였다. 또한 본 연구에서는 기존의 sidewall을 사용하지 않는 새로운 구조를 적용하여 메탈게이트의 사용을 최적화하였고 게이트 절연막으로써 실리콘 옥사이드를 스퍼터링을 이용하여 증착하였기 때문에 저온공정을 성공적으로 수행할 수 있었다. 이러한 게이트 절연막은 열적으로 형성시키지 않고도 70 mv/dec 대의 우수한 subthreshold swing 특성을 보이는 것을 확인하였고, $10^8$정도의 높은 on/off current ratio를 갖는 것을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.1-7
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• 2013

In this paper, a biosensor based on a gated lateral bipolar junction transistor (BJT) is proposed. The gated lateral BJT can function as both a metal-oxide-semiconductor field-effect transistor (MOSFET) and a BJT. By using the self-assembled monolayer (SAM) method, the C-reactive protein antibodies were immobilized on the floating gate of the device as the sensing membrane. Through the experiments, the characteristics of the biosensor were analyzed in this study. According to the results, it is indicated that the gated lateral BJT device can be successfully applied as a biosensor. Additionally, we found that the sensitivity of the gated lateral BJT can be varied by adjusting the emitter (source) bias.

• ETRI Journal
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• v.36 no.5
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• pp.829-834
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• 2014

In this paper, a lateral power metal-oxide-semiconductor field-effect transistor with ultra-low specific on-resistance is proposed to be applied to a high-voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt-implanted p-drift layer assists in the full depletion of the n-drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n-drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in $R_{on.sp}$ and a 16% improvement in BV.

• Journal of Sensor Science and Technology
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• v.19 no.4
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• pp.306-312
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• 2010

We have detected deoxynivalenol(DON) using a metal-oxide-semiconductor field-effect-transistor(MOSFET)-based biosensor. The MOSFET-based biosensor is fabricated by a standard complementary metal-oxide-semiconductor(CMOS) process, and the biosensor's electrical characteristics were investigated. The output of the sensor was stabilized by employing a reference electrode that applies a fixed bias to the gate. Au which has a chemical affinity for thiol was used as the gate metal to immobilize a self-assembled monolayer(SAM) made of 16-mercaptohexadecanoic acid(MHDA). The SAM was used to immobilize anti-deoxynivalenol antibody. The carboxyl group of the SAM was bound to the anti- deoxynivalenol antibody. Anti-deoxynivalenol antibody and deoxynivalenol were bound by an antigen-antibody reaction. In this study, it is confirmed that the MOSFET-based biosensor can detect deoxynivalenol at concentrations as low as 0.1 ${\mu}g$/ml. The measurements were performed in phosphate buffered saline(PBS; pH 7.4) solution. To verify the interaction among the SAM, antibody, and antigen, surface plasmon resonance(SPR) measurements were performed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• Journal of information and communication convergence engineering
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• v.11 no.4
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• pp.288-292
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• 2013

In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage ($V_{th}$) adjustment using a carbon implant significantly improves the $V_{th}$ mismatch performance in a thick (3.3-V) n-MOS transistor. It has been reported that a bad mismatch occurs particularly in the case of 0.11-${\mu}m$ $V_{th}$ node technology. This paper investigates a carbon implant process as a promising candidate for the optimal $V_{th}$ roll-off curve. The carbon implant makes the $V_{th}$ roll-off curve perfectly flat, which is explained in detail. Further, the mechanism of hot carrier injection lifetime degradation by the carbon implant is investigated, and new process integration involving the addition of a nitrogen implant in the lightly doped drain process is offered as its solution. This paper presents the critical side effects, such as Isub increases and device performance shifts caused by the carbon implant and suggests an efficient method to avoid these issues.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.14-22
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• 2010

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.11b
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• pp.204-209
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• 2002

A PDP(Plasma Display Panel) module consists of a discharge panel, a SMPS(Switched Mode Power Supply) for power supply, driving boards for panel control, and a logic board. Driving boards supply high voltage pulses to induce glow discharge in the PDP panel. The electrical pulses excite the circuit elements and subsequently generate acoustic noises. The main sources of the noise in the circuit are the transformer of SMPS and the power MOSFET(Metal Oxide Semiconductor Field Effect Transistor) of driving boards, and the heat sinks often amplify the noise level. The reduction of the acoustic noises was achieved by modifying both the structural and circuit elements. The structural method was executed by the improvement of heat sinks. The optimization of SMPS and condensers was carried out for the circuit elements.